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DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.
On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130005 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1916,6 +1916,42 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
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}
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// (zext x) == C --> x == (trunc C)
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if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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unsigned MinBits = N0.getValueSizeInBits();
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SDValue PreZExt;
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if (N0->getOpcode() == ISD::ZERO_EXTEND) {
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// ZExt
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MinBits = N0->getOperand(0).getValueSizeInBits();
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PreZExt = N0->getOperand(0);
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} else if (N0->getOpcode() == ISD::AND) {
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// DAGCombine turns costly ZExts into ANDs
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
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if ((C->getAPIntValue()+1).isPowerOf2()) {
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MinBits = C->getAPIntValue().countTrailingOnes();
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PreZExt = N0->getOperand(0);
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}
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} else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
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// ZEXTLOAD
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if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
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MinBits = LN0->getMemoryVT().getSizeInBits();
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PreZExt = N0;
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}
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}
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// Make sure we're not loosing bits from the constant.
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if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
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EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
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if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
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// Will get folded away.
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
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SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
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return DAG.getSetCC(dl, VT, Trunc, C, Cond);
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}
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}
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}
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// If the LHS is '(and load, const)', the RHS is 0,
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// the test is for equality or unsigned, and all 1 bits of the const are
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// in the same partial word, see if we can shorten the load.
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@ -2259,34 +2259,6 @@ icmp transform.
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//===---------------------------------------------------------------------===//
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These functions:
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int foo(int *X) {
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if ((*X & 255) == 47)
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bar();
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}
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int foo2(int X) {
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if ((X & 255) == 47)
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bar();
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}
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codegen to:
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movzbl (%rdi), %eax
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cmpl $47, %eax
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jne LBB0_2
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and:
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movzbl %dil, %eax
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cmpl $47, %eax
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jne LBB1_2
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If a dag combine shrunk the compare to a byte compare, then we'd fold the load
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in the first example, and eliminate the movzbl in the second, saving a register.
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This can be a target independent dag combine that works on ISD::SETCC, it would
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catch this before the legalize ops pass.
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//===---------------------------------------------------------------------===//
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We should optimize this:
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%tmp = load i16* %arrayidx, align 4, !tbaa !0
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@ -2329,8 +2301,7 @@ Index: InstCombine/InstCombineCompares.cpp
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{
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but we can't do that until the dag combine above is added. Not having this
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is blocking resolving PR6627.
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Not having this is blocking resolving PR6627.
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//===---------------------------------------------------------------------===//
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36
test/CodeGen/X86/shrink-compare.ll
Normal file
36
test/CodeGen/X86/shrink-compare.ll
Normal file
@ -0,0 +1,36 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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declare void @bar()
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define void @test1(i32* nocapture %X) nounwind {
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entry:
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%tmp1 = load i32* %X, align 4
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%and = and i32 %tmp1, 255
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%cmp = icmp eq i32 %and, 47
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @bar() nounwind
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br label %if.end
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if.end:
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ret void
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; CHECK: test1:
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; CHECK: cmpb $47, (%rdi)
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}
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define void @test2(i32 %X) nounwind {
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entry:
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%and = and i32 %X, 255
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%cmp = icmp eq i32 %and, 47
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @bar() nounwind
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br label %if.end
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if.end:
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ret void
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; CHECK: test2:
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; CHECK: cmpb $47, %dil
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}
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