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Disengage DEBUG_LOC from non-PPC targets.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2005-12-21 20:51:37 +00:00
parent e892a55e90
commit e81aecbae6
8 changed files with 31 additions and 13 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -622,6 +622,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) {
MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
std::vector<SDOperand> Ops;
Ops.push_back(Tmp1); // chain
@ -634,6 +635,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
unsigned id = DebugInfo.RecordSource(fname, dirname);
Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
} else {
Result = Tmp1; // chain
}
Result = LegalizeOp(Result); // Relegalize new nodes.
break;
}

1
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -102,6 +102,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
addLegalFPImmediate(+0.0); //F31
addLegalFPImmediate(-0.0); //-F31

1
lib/Target/IA64/IA64ISelLowering.cpp
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@ -74,6 +74,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);

1
lib/Target/IA64/IA64ISelPattern.cpp
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@ -102,6 +102,7 @@ namespace {
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();

5
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -147,6 +147,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}

5
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
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@ -147,6 +147,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}

1
lib/Target/X86/X86ISelLowering.cpp
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@ -126,6 +126,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.