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Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1793,8 +1793,6 @@ public:
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void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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int32_t Imm = Memory.OffsetImm->getValue();
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// FIXME: Handle #-0
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if (Imm == INT32_MIN) Imm = 0;
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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@ -778,8 +778,10 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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} else {
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Reg = ARM::PC;
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int32_t Offset = MO.getImm();
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// FIXME: Handle #-0.
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if (Offset < 0) {
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if (Offset == INT32_MIN) {
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Offset = 0;
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isAdd = false;
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} else if (Offset < 0) {
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Offset *= -1;
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isAdd = false;
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}
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@ -830,6 +830,18 @@ _func:
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@ CHECK: ldr.w pc, [pc, #256] @ encoding: [0xdf,0xf8,0x00,0xf1]
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@ CHECK: ldr.w pc, [pc, #-400] @ encoding: [0x5f,0xf8,0x90,0xf1]
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ldrb r9, [pc, #-0]
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ldrsb r11, [pc, #-0]
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ldrh r10, [pc, #-0]
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ldrsh r1, [pc, #-0]
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ldr r5, [pc, #-0]
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@ CHECK: ldrb.w r9, [pc, #-0] @ encoding: [0x1f,0xf8,0x00,0x90]
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@ CHECK: ldrsb.w r11, [pc, #-0] @ encoding: [0x1f,0xf9,0x00,0xb0]
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@ CHECK: ldrh.w r10, [pc, #-0] @ encoding: [0x3f,0xf8,0x00,0xa0]
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@ CHECK: ldrsh.w r1, [pc, #-0] @ encoding: [0x3f,0xf9,0x00,0x10]
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@ CHECK: ldr.w r5, [pc, #-0] @ encoding: [0x5f,0xf8,0x00,0x50]
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@------------------------------------------------------------------------------
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@ LDR(register)
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@------------------------------------------------------------------------------
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