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* Fix nonconstant shift case

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* Turn table into 2d table


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-11-02 01:41:55 +00:00
parent 8b6c5e4412
commit e9913f2cff
2 changed files with 38 additions and 108 deletions
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73
lib/Target/X86/InstSelectSimple.cpp
View File

@ -172,8 +172,8 @@ ISel::visitShiftInst (ShiftInst & I)
{ {
unsigned Op0r = getReg (I.getOperand (0)); unsigned Op0r = getReg (I.getOperand (0));
unsigned DestReg = getReg (I); unsigned DestReg = getReg (I);
bool isRightShift = (I.getOpcode () == Instruction::Shr); bool isLeftShift = I.getOpcode() == Instruction::Shl;
bool isOperandUnsigned = I.getType ()->isUnsigned (); bool isOperandSigned = I.getType()->isUnsigned();
unsigned OperandClass = getClass(I.getType()); unsigned OperandClass = getClass(I.getType());
if (OperandClass > 2) if (OperandClass > 2)
@ -185,31 +185,15 @@ ISel::visitShiftInst (ShiftInst & I)
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
unsigned char shAmt = CUI->getValue(); unsigned char shAmt = CUI->getValue();
// This is a shift right (SHR). static const unsigned ConstantOperand[][4] = {
static const unsigned SHRUnsignedConstantOperand[] = { { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
X86::SHRir8, X86::SHRir16, X86::SHRir32 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
}; };
// This is a shift right arithmetic (SAR). const unsigned *OpTab = // Figure out the operand table to use
static const unsigned SHRSignedConstantOperand[] = { ConstantOperand[isLeftShift*2+isOperandSigned];
X86::SARir8, X86::SARir16, X86::SARir32
};
// This is a shift left (SHL).
static const unsigned SHLConstantOperand[] = {
X86::SHLir8, X86::SHLir16, X86::SHLir32
};
const unsigned *OpTab = 0; // Figure out the operand table to use
if (isRightShift) {
if (isOperandUnsigned)
OpTab = SHRUnsignedConstantOperand;
else
OpTab = SHRSignedConstantOperand;
} else {
// This is a left shift (SHL).
OpTab = SHLConstantOperand;
}
// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.) // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt); BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
@ -222,41 +206,22 @@ ISel::visitShiftInst (ShiftInst & I)
// that amount is already in the CL register, so we have to put it // that amount is already in the CL register, so we have to put it
// there first. // there first.
// //
// Get it from the register it's in.
unsigned Op1r = getReg (I.getOperand (1));
// Emit: move cl, shiftAmount (put the shift amount in CL.) // Emit: move cl, shiftAmount (put the shift amount in CL.)
BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r); BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg(getReg(I.getOperand(1)));
// This is a shift right (SHR). // This is a shift right (SHR).
static const unsigned SHRUnsignedOperand[] = { static const unsigned NonConstantOperand[][4] = {
X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
{ X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
}; };
// This is a shift right arithmetic (SAR). const unsigned *OpTab = // Figure out the operand table to use
static const unsigned SHRSignedOperand[] = { NonConstantOperand[isLeftShift*2+isOperandSigned];
X86::SARrr8, X86::SARrr16, X86::SARrr32
};
// This is a shift left (SHL). BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
static const unsigned SHLOperand[] = {
X86::SHLrr8, X86::SHLrr16, X86::SHLrr32
};
// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
const unsigned *OpTab = 0; // Figure out the operand table to use
if (isRightShift) {
if (isOperandUnsigned)
OpTab = SHRUnsignedOperand;
else
OpTab = SHRSignedOperand;
} else {
// This is a left shift (SHL).
OpTab = SHLOperand;
}
BuildMI (BB, X86::SHLrr32, 2,
DestReg).addReg (Op0r).addReg (X86::CL);
} }
} }

73
lib/Target/X86/X86ISelSimple.cpp
View File

@ -172,8 +172,8 @@ ISel::visitShiftInst (ShiftInst & I)
{ {
unsigned Op0r = getReg (I.getOperand (0)); unsigned Op0r = getReg (I.getOperand (0));
unsigned DestReg = getReg (I); unsigned DestReg = getReg (I);
bool isRightShift = (I.getOpcode () == Instruction::Shr); bool isLeftShift = I.getOpcode() == Instruction::Shl;
bool isOperandUnsigned = I.getType ()->isUnsigned (); bool isOperandSigned = I.getType()->isUnsigned();
unsigned OperandClass = getClass(I.getType()); unsigned OperandClass = getClass(I.getType());
if (OperandClass > 2) if (OperandClass > 2)
@ -185,31 +185,15 @@ ISel::visitShiftInst (ShiftInst & I)
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
unsigned char shAmt = CUI->getValue(); unsigned char shAmt = CUI->getValue();
// This is a shift right (SHR). static const unsigned ConstantOperand[][4] = {
static const unsigned SHRUnsignedConstantOperand[] = { { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
X86::SHRir8, X86::SHRir16, X86::SHRir32 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
}; };
// This is a shift right arithmetic (SAR). const unsigned *OpTab = // Figure out the operand table to use
static const unsigned SHRSignedConstantOperand[] = { ConstantOperand[isLeftShift*2+isOperandSigned];
X86::SARir8, X86::SARir16, X86::SARir32
};
// This is a shift left (SHL).
static const unsigned SHLConstantOperand[] = {
X86::SHLir8, X86::SHLir16, X86::SHLir32
};
const unsigned *OpTab = 0; // Figure out the operand table to use
if (isRightShift) {
if (isOperandUnsigned)
OpTab = SHRUnsignedConstantOperand;
else
OpTab = SHRSignedConstantOperand;
} else {
// This is a left shift (SHL).
OpTab = SHLConstantOperand;
}
// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.) // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt); BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
@ -222,41 +206,22 @@ ISel::visitShiftInst (ShiftInst & I)
// that amount is already in the CL register, so we have to put it // that amount is already in the CL register, so we have to put it
// there first. // there first.
// //
// Get it from the register it's in.
unsigned Op1r = getReg (I.getOperand (1));
// Emit: move cl, shiftAmount (put the shift amount in CL.) // Emit: move cl, shiftAmount (put the shift amount in CL.)
BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r); BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg(getReg(I.getOperand(1)));
// This is a shift right (SHR). // This is a shift right (SHR).
static const unsigned SHRUnsignedOperand[] = { static const unsigned NonConstantOperand[][4] = {
X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
{ X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
}; };
// This is a shift right arithmetic (SAR). const unsigned *OpTab = // Figure out the operand table to use
static const unsigned SHRSignedOperand[] = { NonConstantOperand[isLeftShift*2+isOperandSigned];
X86::SARrr8, X86::SARrr16, X86::SARrr32
};
// This is a shift left (SHL). BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
static const unsigned SHLOperand[] = {
X86::SHLrr8, X86::SHLrr16, X86::SHLrr32
};
// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
const unsigned *OpTab = 0; // Figure out the operand table to use
if (isRightShift) {
if (isOperandUnsigned)
OpTab = SHRUnsignedOperand;
else
OpTab = SHRSignedOperand;
} else {
// This is a left shift (SHL).
OpTab = SHLOperand;
}
BuildMI (BB, X86::SHLrr32, 2,
DestReg).addReg (Op0r).addReg (X86::CL);
} }
} }