RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-10 22:46:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-08-10 16:20:33 +00:00
parent c038ba915e
commit e9a09933ef
6 changed files with 0 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
View File

@ -1660,7 +1660,6 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
case Hexagon::CONST32:
case Hexagon::CONST32_Float_Real:
case Hexagon::CONST32_Int_Real:
case Hexagon::FCONST32_nsdata:
is32bit = true;
// Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
case Hexagon::CONST64_Float_Real:

1
lib/Target/Hexagon/HexagonAsmPrinter.cpp
View File

@ -305,7 +305,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
case Hexagon::CONST32:
case Hexagon::CONST32_Float_Real:
case Hexagon::CONST32_Int_Real:
case Hexagon::FCONST32_nsdata:
if (!OutStreamer->hasRawTextSupport()) {
MCOperand &Imm = MappedInst.getOperand(1);
MCSectionSubPair Current = OutStreamer->getCurrentSection();

2
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -2215,7 +2215,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
@ -2230,7 +2229,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
case HexagonISD::INSERT: return "HexagonISD::INSERT";
case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
case HexagonISD::JT: return "HexagonISD::JT";

2
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -31,9 +31,7 @@ bool isPositiveHalfWord(SDNode *N);
CONST32 = OP_BEGIN,
CONST32_GP, // For marking data present in GP.
FCONST32,
ALLOCA,
ARGEXTEND,
AT_GOT, // Index in GOT.
AT_PCREL, // Offset relative to PC.

12
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -5127,18 +5127,6 @@ def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
let isCodeGenOnly = 1 in
def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = $src1",
[(set (i32 IntRegs:$dst),
(Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
let AddedComplexity = 100 in
def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
(i32 IntRegs:$src1)>;
def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;

11
lib/Target/Hexagon/HexagonInstrInfoV5.td
View File

@ -67,17 +67,6 @@ def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
let Inst{20,13,7,4} = 0b1111;
}
def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>,
SDTCisPtrTy<1>]>;
def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst = CONST32(#$global)",
[(set F32:$dst,
(HexagonFCONST32 tglobaladdr:$global))]>,
Requires<[HasV5T]>;
let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
"$dst = CONST64(#$src1)",