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Changed the CreateCodeToLoadConst function to preserve SSA form. This basically means adding extra tmp instructions for intermediate values.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner 2004-11-23 04:22:29 +00:00
parent f2190b39d0
commit e9cf6b9278
1 changed files with 24 additions and 7 deletions
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31
lib/Target/SparcV9/SparcV9BurgISel.cpp
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@ -1111,22 +1111,39 @@ void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
MI->getOperand(0).markHi64();
mvec.push_back(MI);
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
.addRegDef(tmpReg);
.addRegDef(tmpReg2);
MI->getOperand(1).markLo64();
mvec.push_back(MI);
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
.addRegDef(tmpReg));
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg2).addZImm(32)
.addRegDef(tmpReg3));
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg).addRegDef(addrReg);
// Create another TmpInstruction for the address register
TmpInstruction* addrReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg3).addRegDef(addrReg2);
mvec.push_back(MI);
MI = BuildMI(V9::ORi, 3).addReg(addrReg).addConstantPoolIndex(CPI)
.addRegDef(addrReg);
// Create another TmpInstruction for the address register
TmpInstruction* addrReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
MI = BuildMI(V9::ORi, 3).addReg(addrReg2).addConstantPoolIndex(CPI)
.addRegDef(addrReg3);
MI->getOperand(1).markLo32();
mvec.push_back(MI);
@ -1134,7 +1151,7 @@ void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
unsigned Opcode = ChooseLoadInstruction(val->getType());
Opcode = convertOpcodeFromRegToImm(Opcode);
mvec.push_back(BuildMI(Opcode, 3)
.addReg(addrReg).addSImm((int64_t)0).addRegDef(dest));
.addReg(addrReg3).addSImm((int64_t)0).addRegDef(dest));
}
}