RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-05 19:29:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Implement @llvm.readcyclecounter()

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295892 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-02-22 22:28:47 +00:00
parent 206dfa3c0d
commit e9d7ca1b92
7 changed files with 44 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -556,7 +556,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
/* 0 */ SA0, LC0, SA1, LC1,
/* 4 */ P3_0, C5, C6, C7,
/* 8 */ USR, PC, UGP, GP,
/* 12 */ CS0, CS1, UPCL, UPCH,
/* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
/* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
/* 20 */ 0, 0, 0, 0,
/* 24 */ 0, 0, 0, 0,
@ -583,7 +583,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
/* 0 */ C1_0, 0, C3_2, 0,
/* 4 */ C5_4, 0, C7_6, 0,
/* 8 */ C9_8, 0, C11_10, 0,
/* 12 */ CS, 0, UPC, 0,
/* 12 */ CS, 0, UPCYCLE, 0,
/* 16 */ C17_16, 0, PKTCOUNT, 0,
/* 20 */ 0, 0, 0, 0,
/* 24 */ 0, 0, 0, 0,

15
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1062,6 +1062,18 @@ SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
}
// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
// is marked as having side-effects, while the register read on Hexagon does
// not have any. TableGen refuses to accept the direct pattern from that node
// to the A4_tfrcpp.
SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDLoc dl(Op);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
}
SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
@ -1828,6 +1840,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
@ -2303,6 +2316,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
case HexagonISD::OP_END: break;
}
return nullptr;
@ -2980,6 +2994,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
}
}

2
lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -86,6 +86,7 @@ namespace HexagonISD {
TC_RETURN,
EH_RETURN,
DCFETCH,
READCYCLE,
OP_END
};
@ -146,6 +147,7 @@ namespace HexagonISD {
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
SDValue

8
lib/Target/Hexagon/HexagonPatterns.td
View File

@ -3338,3 +3338,11 @@ def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)),
def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)),
(S2_vsxthw (LoReg (v4i16 (S2_vsxtbh (L2_loadrh_io I32:$Rs, 0)))))>;
// Read cycle counter.
//
def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf,
[SDNPHasChain]>;
def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;

4
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -161,8 +161,8 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
Reserved.set(Hexagon::GP); // C11
Reserved.set(Hexagon::CS0); // C12
Reserved.set(Hexagon::CS1); // C13
Reserved.set(Hexagon::UPCL); // C14
Reserved.set(Hexagon::UPCH); // C15
Reserved.set(Hexagon::UPCYCLELO); // C14
Reserved.set(Hexagon::UPCYCLEHI); // C15
Reserved.set(Hexagon::FRAMELIMIT); // C16
Reserved.set(Hexagon::FRAMEKEY); // C17
Reserved.set(Hexagon::PKTCOUNTLO); // C18

10
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -162,8 +162,8 @@ let Namespace = "Hexagon" in {
def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>;
def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>;
def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>;
def UPCL: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>;
def UPCH: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>;
def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>;
def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>;
def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>;
@ -182,7 +182,7 @@ let Namespace = "Hexagon" in {
def C9_8: Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>;
def C11_10: Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>;
def CS: Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>;
def UPC: Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>;
def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI]>, DwarfRegNum<[80]>;
def C17_16: Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>;
def PKTCOUNT: Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>,
DwarfRegNum<[85]>;
@ -281,7 +281,7 @@ def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
let Size = 32, isAllocatable = 0 in
def CtrRegs : RegisterClass<"Hexagon", [i32], 32,
(add LC0, SA0, LC1, SA1, P3_0, C5, C6, C7,
C8, PC, UGP, GP, CS0, CS1, UPCL, UPCH,
C8, PC, UGP, GP, CS0, CS1, UPCYCLELO, UPCYCLEHI,
FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI,
M0, M1, USR)>;
@ -290,7 +290,7 @@ def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>;
let Size = 64, isAllocatable = 0 in
def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
(add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPC, C17_16,
(add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16,
PKTCOUNT, UTIMER)>;
// These registers are new for v62 and onward.

10
test/CodeGen/Hexagon/readcyclecounter.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-LABEL: test_readcyclecounter
; CHECK: r1:0 = c15:14
define i64 @test_readcyclecounter() nounwind {
%t0 = call i64 @llvm.readcyclecounter()
ret i64 %t0
}
declare i64 @llvm.readcyclecounter()