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The preferred alignment defaults to the abi alignment. Omit if it is the same.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197400 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2013-12-16 18:01:51 +00:00
parent 63da3bbcf5
commit ea53c6ae30
11 changed files with 19 additions and 19 deletions
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2
lib/Target/AArch64/AArch64TargetMachine.cpp
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@ -34,7 +34,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
InstrInfo(Subtarget),
DL("e-i64:64:64-i128:128:128-s:32:32-n32:64-S128"),
DL("e-i64:64-i128:128-s:32-n32:64-S128"),
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {

2
lib/Target/ARM/ARMTargetMachine.cpp
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@ -77,7 +77,7 @@ static std::string computeDataLayout(ARMSubtarget &ST) {
if (ST.isAPCS_ABI())
Ret += "-f64:32:64";
else
Ret += "-i64:64:64";
Ret += "-i64:64";
// On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
// align to 32.

2
lib/Target/Hexagon/HexagonTargetMachine.cpp
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@ -71,7 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DL("e-p:32:32:32-i64:64:64-i1:32:32-a:0-n32") ,
DL("e-p:32:32-i64:64-i1:32-a:0-n32") ,
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget),

2
lib/Target/MSP430/MSP430TargetMachine.cpp
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@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
// FIXME: Check DataLayout string.
DL("e-p:16:16:16-i32:16:32-n8:16"),
DL("e-p:16:16-i32:16:32-n8:16"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();

4
lib/Target/Mips/MipsTargetMachine.cpp
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@ -56,11 +56,11 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
// Pointers are 32 bit on some ABIs.
if (!ST.isABI_N64())
Ret += "-p:32:32:32";
Ret += "-p:32:32";
// 8 and 16 bit integers only need no have natural alignment, but try to
// align them to 32 bits. 64 bit integers have natural alignment.
Ret += "-i8:8:32-i16:16:32-i64:64:64";
Ret += "-i8:8:32-i16:16:32-i64:64";
// 32 bit registers are always available and the stack is at least 64 bit
// aligned. On N64 64 bit registers are also available and the stack is

4
lib/Target/NVPTX/NVPTXTargetMachine.cpp
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@ -67,9 +67,9 @@ static std::string computeDataLayout(const NVPTXSubtarget &ST) {
std::string Ret = "e";
if (!ST.is64Bit())
Ret += "-p:32:32:32";
Ret += "-p:32:32";
Ret += "-i64:64:64-v16:16:16-v32:32:32-n16:32:64";
Ret += "-i64:64-v16:16-v32:32-n16:32:64";
return Ret;
}

2
lib/Target/PowerPC/PPCTargetMachine.cpp
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@ -44,7 +44,7 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
Ret += "-i64:64:64";
Ret += "-i64:64";
// Set support for 128 floats depending on the ABI.
if (!ST.isPPC64() || !ST.isSVR4ABI())

6
lib/Target/R600/AMDGPUTargetMachine.cpp
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@ -51,13 +51,13 @@ SchedCustomRegistry("r600", "Run R600's custom scheduler",
static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
std::string DataLayout = std::string(
"e-i64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v96:128:128"
"-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048"
"-n32:64"
);
if (!ST.is64bit())
DataLayout.append("-p:32:32:32");
DataLayout.append("-p:32:32");
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
DataLayout.append("-p3:32:32:32");

6
lib/Target/Sparc/SparcTargetMachine.cpp
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@ -29,17 +29,17 @@ static std::string computeDataLayout(const SparcSubtarget &ST) {
// Some ABIs have 32bit pointers.
if (!ST.is64Bit())
Ret += "-p:32:32:32";
Ret += "-p:32:32";
// Alignments for 64 bit integers.
Ret += "-i64:64:64";
Ret += "-i64:64";
// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
if (ST.is64Bit())
Ret += "-n32:64";
else
Ret += "-f128:64:64-n32";
Ret += "-f128:64-n32";
return Ret;
}

6
lib/Target/X86/X86TargetMachine.cpp
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@ -45,15 +45,15 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
Ret += "-i64:64:64";
Ret += "-i64:64";
else
Ret += "-f64:32:64";
// Some ABIs align long double to 128 bits, others to 32.
if (ST.is64Bit() || ST.isTargetDarwin())
Ret += "-f80:128:128";
Ret += "-f80:128";
else
Ret += "-f80:32:32";
Ret += "-f80:32";
// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
if (ST.is64Bit())

2
lib/Target/XCore/XCoreTargetMachine.cpp
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@ -27,7 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
DL("e-p:32:32:32-a:0:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32:32-n32"),
DL("e-p:32:32-a:0:32-f64:32-i1:8:32-i8:8:32-i16:16:32-i64:32-n32"),
InstrInfo(),
FrameLowering(Subtarget),
TLInfo(*this),