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Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2009-04-29 22:47:44 +00:00
parent eb3948be16
commit ec8eee2d3a
5 changed files with 22 additions and 52 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3946,8 +3946,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the vector input.
Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
LegalizeOp(Node->getOperand(0)));
Tmp1 = LegalizeOp(Node->getOperand(0));
Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1);
break;
} else if (NumElems == 1) {
// Turn this into a bit convert of the scalar input.

43
lib/Target/X86/X86ISelLowering.cpp
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@ -2884,44 +2884,6 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
}
/// isVectorLoad - Returns true if the node is a vector load, a scalar
/// load that's promoted to vector, or a load bitcasted.
static bool isVectorLoad(SDValue Op) {
assert(Op.getValueType().isVector() && "Expected a vector type");
if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
Op.getOpcode() == ISD::BIT_CONVERT) {
return isa<LoadSDNode>(Op.getOperand(0));
}
return isa<LoadSDNode>(Op);
}
/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
///
static SDValue CanonicalizeMovddup(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
bool HasSSE3) {
// If we have sse3 and shuffle has more than one use or input is a load, then
// use movddup. Otherwise, use movlhps.
SDValue V1 = SV->getOperand(0);
bool UseMovddup = HasSSE3 && (!SV->hasOneUse() || isVectorLoad(V1));
MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
MVT VT = SV->getValueType(0);
if (VT == PVT)
return SDValue(SV, 0);
DebugLoc dl = SV->getDebugLoc();
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
if (PVT.getVectorNumElements() == 2) {
int Mask[2] = { 0, 0 };
V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
} else {
int Mask[4] = { 0, 1, 0, 1 };
V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
}
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
}
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
/// vector of zero or undef vector. This produces a shuffle where the low
/// element of V2 is swizzled into the zero/undef vector, landing at element
@ -3977,11 +3939,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (isZeroShuffle(SVOp))
return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
// Canonicalize movddup shuffles.
if (V2IsUndef && Subtarget->hasSSE2() && VT.getSizeInBits() == 128 &&
X86::isMOVDDUPMask(SVOp))
return CanonicalizeMovddup(SVOp, DAG, Subtarget->hasSSE3());
// Promote splats to v4f32.
if (SVOp->isSplat()) {
if (isMMX || NumElems < 4)

16
lib/Target/X86/X86InstrSSE.td
View File

@ -748,10 +748,12 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:
} // AddedComplexity
} // Constraints = "$src1 = $dst"
let AddedComplexity = 20 in
let AddedComplexity = 20 in {
def : Pat<(v4f32 (movddup VR128:$src, (undef))),
(MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
def : Pat<(v2i64 (movddup VR128:$src, (undef))),
(MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
}
@ -2430,9 +2432,17 @@ def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
(undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
let AddedComplexity = 5 in {
def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
}
// Arithmetic
let Constraints = "$src1 = $dst" in {

9
test/CodeGen/X86/vec_shuffle-22.ll
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@ -1,6 +1,9 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shuf
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse3 | grep movlhps | count 2
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse3 | grep movddup | count 1
; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium-m -o %t -f
; RUN: grep movlhps %t | count 1
; RUN: grep pshufd %t | count 1
; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
; RUN: grep movlhps %t | count 1
; RUN: grep movddup %t | count 1
define <4 x float> @t1(<4 x float> %a) nounwind {
entry:

2
test/CodeGen/X86/vec_shuffle.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
; RUN: grep shufp %t | count 1
; RUN: grep movupd %t | count 1
; RUN: grep pshufhw %t | count 1