mirror of
https://github.com/RPCS3/llvm.git
synced 2025-04-02 05:12:20 +00:00
implement a bunch more intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27209 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
858b35eaf7
commit
ecc219b8d4
@ -69,16 +69,19 @@ def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
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let isLoad = 1, PPC970_Unit = 2 in { // Loads.
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
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"lvebx $vD, $src", LdStGeneral,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
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"lvehx $vD, $src", LdStGeneral,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
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"lvewx $vD, $src", LdStGeneral,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
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"lvx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
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[(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
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def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
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"lvxl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
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}
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
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@ -100,7 +103,10 @@ def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
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[(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
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def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
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"stvx $rS, $dst", LdStGeneral,
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[(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
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[(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
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def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
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"stvxl $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
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}
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let PPC970_Unit = 5 in { // VALU Operations.
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@ -197,10 +203,10 @@ def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[]>;
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def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
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"vexptefp $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
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def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
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"vlogefp $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
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def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmaxfp $vD, $vA, $vB", VecFP,
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[]>;
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@ -209,19 +215,19 @@ def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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[]>;
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def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
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"vrefp $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
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def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
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"vrfim $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrfim VRRC:$vB))]>;
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def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
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"vrfin $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrfin VRRC:$vB))]>;
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def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
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"vrfip $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrfip VRRC:$vB))]>;
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def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
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"vrfiz $vD, $vB", VecFP,
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[]>;
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[(set VRRC:$vD, (int_ppc_altivec_vrfiz VRRC:$vB))]>;
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def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
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"vrsqrtefp $vD, $vB", VecFP,
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[(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
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@ -268,7 +274,28 @@ def VSUBUWS : VXForm_1<1664, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubuws $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
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def VSUMSWS : VXForm_1<1928, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsumsws $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsumsws VRRC:$vA, VRRC:$vB))]>;
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def VSUM2SWS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsum2sws $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsum2sws VRRC:$vA, VRRC:$vB))]>;
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def VSUM4SBS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsum4sbs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsum4sbs VRRC:$vA, VRRC:$vB))]>;
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def VSUM4SHS: VXForm_1<1608, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsum4shs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsum4shs VRRC:$vA, VRRC:$vB))]>;
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def VSUM4UBS: VXForm_1<1544, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsum4ubs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsum4ubs VRRC:$vA, VRRC:$vB))]>;
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def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vnor $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
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@ -279,6 +306,36 @@ def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VRLB : VXForm_1<4, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlb VRRC:$vA, VRRC:$vB))]>;
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def VRLH : VXForm_1<68, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlh VRRC:$vA, VRRC:$vB))]>;
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def VRLW : VXForm_1<132, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vrlw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vrlw VRRC:$vA, VRRC:$vB))]>;
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def VSLO : VXForm_1<1036, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslo $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslo VRRC:$vA, VRRC:$vB))]>;
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def VSLB : VXForm_1<260, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslb VRRC:$vA, VRRC:$vB))]>;
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def VSLH : VXForm_1<324, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslh VRRC:$vA, VRRC:$vB))]>;
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def VSLW : VXForm_1<388, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vslw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vslw VRRC:$vA, VRRC:$vB))]>;
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def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltb $vD, $vB, $UIMM", VecPerm,
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[]>;
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@ -290,6 +347,40 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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def VSR : VXForm_1<708, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsr $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsr VRRC:$vA, VRRC:$vB))]>;
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def VSRO : VXForm_1<1100, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsro $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsro VRRC:$vA, VRRC:$vB))]>;
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def VSRAB : VXForm_1<772, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrab $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrab VRRC:$vA, VRRC:$vB))]>;
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def VSRAH : VXForm_1<836, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrah $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrah VRRC:$vA, VRRC:$vB))]>;
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def VSRAW : VXForm_1<900, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsraw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsraw VRRC:$vA, VRRC:$vB))]>;
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def VSRB : VXForm_1<516, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrb $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrb VRRC:$vA, VRRC:$vB))]>;
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def VSRH : VXForm_1<580, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrh $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrh VRRC:$vA, VRRC:$vB))]>;
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def VSRW : VXForm_1<644, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsrw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsrw VRRC:$vA, VRRC:$vB))]>;
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def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisb $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
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@ -436,6 +527,7 @@ def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
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def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
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def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
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def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
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def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
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// Stores.
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def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
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@ -444,6 +536,8 @@ def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
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(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
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def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
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(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
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def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
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(STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
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// Bit conversions.
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def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
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@ -50,14 +50,9 @@ altivec instructions. Examples
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Missing intrinsics:
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ds*
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lve*
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lvs*
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lvx*
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lvsl/lvsr
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mf*
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st*
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vavg*
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vexptefp
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vlogefp
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vmax*
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vmhaddshs/vmhraddshs
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vmin*
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@ -67,11 +62,7 @@ vmsum*
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vmul*
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vperm
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vpk*
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vr*
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vsel (some aliases only accessible using builtins)
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vsl* (except vsldoi)
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vsr*
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vsum*
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vup*
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//===----------------------------------------------------------------------===//
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