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Thumb assembly parsing and encoding for LDR(immediate) form T2.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-19 18:13:48 +00:00
parent 2f7232efd5
commit ecd8589683
3 changed files with 25 additions and 1 deletions
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2
lib/Target/ARM/ARMInstrThumb.td
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@ -189,11 +189,13 @@ def t_addrmode_is1 : Operand<i32>,
// t_addrmode_sp := sp + imm8 * 4 // t_addrmode_sp := sp + imm8 * 4
// //
def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
def t_addrmode_sp : Operand<i32>, def t_addrmode_sp : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
let EncoderMethod = "getAddrModeThumbSPOpValue"; let EncoderMethod = "getAddrModeThumbSPOpValue";
let DecoderMethod = "DecodeThumbAddrModeSP"; let DecoderMethod = "DecodeThumbAddrModeSP";
let PrintMethod = "printThumbAddrModeSPOperand"; let PrintMethod = "printThumbAddrModeSPOperand";
let ParserMatchClass = t_addrmode_sp_asm_operand;
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
} }

17
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -626,7 +626,15 @@ public:
// Immediate offset, multiple of 4 in range [0, 124]. // Immediate offset, multiple of 4 in range [0, 124].
if (!Mem.OffsetImm) return true; if (!Mem.OffsetImm) return true;
int64_t Val = Mem.OffsetImm->getValue(); int64_t Val = Mem.OffsetImm->getValue();
return Val >= 0 && Val < 125 && (Val % 4) == 0; return Val >= 0 && Val <= 124 && (Val % 4) == 0;
}
bool isMemThumbSPI() const {
if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
return false;
// Immediate offset, multiple of 4 in range [0, 1020].
if (!Mem.OffsetImm) return true;
int64_t Val = Mem.OffsetImm->getValue();
return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
} }
bool isMemImm8Offset() const { bool isMemImm8Offset() const {
if (Kind != Memory || Mem.OffsetRegNum != 0) if (Kind != Memory || Mem.OffsetRegNum != 0)
@ -992,6 +1000,13 @@ public:
Inst.addOperand(MCOperand::CreateImm(Val)); Inst.addOperand(MCOperand::CreateImm(Val));
} }
void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
Inst.addOperand(MCOperand::CreateImm(Val));
}
void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());

7
test/MC/ARM/basic-thumb-instructions.s
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@ -182,8 +182,15 @@ _func:
ldr r1, [r5] ldr r1, [r5]
ldr r2, [r6, #32] ldr r2, [r6, #32]
ldr r3, [r7, #124] ldr r3, [r7, #124]
ldr r1, [sp]
ldr r2, [sp, #24]
ldr r3, [sp, #1020]
@ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68] @ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68]
@ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a] @ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a]
@ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f] @ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f]
@ CHECK: ldr r1, [sp] @ encoding: [0x00,0x99]
@ CHECK: ldr r2, [sp, #24] @ encoding: [0x06,0x9a]
@ CHECK: ldr r3, [sp, #1020] @ encoding: [0xff,0x9b]