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Decouple MCInstBuilder from the streamer per Eli's request.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2012-11-26 18:05:52 +00:00
parent 70af909f67
commit ed9e442cf0
4 changed files with 113 additions and 160 deletions
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6
include/llvm/MC/MCInstBuilder.h
View File

@ -16,7 +16,6 @@
#define LLVM_MC_MCINSTBUILDER_H #define LLVM_MC_MCINSTBUILDER_H
#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInst.h"
#include "llvm/MC/MCStreamer.h"
namespace llvm { namespace llvm {
@ -59,9 +58,8 @@ public:
return *this; return *this;
} }
/// \brief Emit the built instruction to an MCStreamer. operator MCInst&() {
void emit(MCStreamer &OutStreamer) { return Inst;
OutStreamer.EmitInstruction(Inst);
} }
}; };

192
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1052,11 +1052,10 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
OutContext); OutContext);
// If this isn't a TBB or TBH, the entries are direct branch instructions. // If this isn't a TBB or TBH, the entries are direct branch instructions.
if (OffsetWidth == 4) { if (OffsetWidth == 4) {
MCInstBuilder(ARM::t2B) OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
.addExpr(MBBSymbolExpr) .addExpr(MBBSymbolExpr)
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
continue; continue;
} }
// Otherwise it's an offset from the dispatch instruction. Construct an // Otherwise it's an offset from the dispatch instruction. Construct an
@ -1277,15 +1276,15 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
case ARM::t2LEApcrel: { case ARM::t2LEApcrel: {
// FIXME: Need to also handle globals and externals // FIXME: Need to also handle globals and externals
MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
ARM::t2LEApcrel ? ARM::t2ADR
: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
: ARM::ADR)) : ARM::ADR))
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext)) .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
// Add predicate operands. // Add predicate operands.
.addImm(MI->getOperand(2).getImm()) .addImm(MI->getOperand(2).getImm())
.addReg(MI->getOperand(3).getReg()) .addReg(MI->getOperand(3).getReg()));
.emit(OutStreamer);
return; return;
} }
case ARM::LEApcrelJT: case ARM::LEApcrelJT:
@ -1294,94 +1293,86 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCSymbol *JTIPICSymbol = MCSymbol *JTIPICSymbol =
GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
MI->getOperand(2).getImm()); MI->getOperand(2).getImm());
MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
ARM::t2LEApcrelJT ? ARM::t2ADR
: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
: ARM::ADR)) : ARM::ADR))
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext)) .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
// Add predicate operands. // Add predicate operands.
.addImm(MI->getOperand(3).getImm()) .addImm(MI->getOperand(3).getImm())
.addReg(MI->getOperand(4).getReg()) .addReg(MI->getOperand(4).getReg()));
.emit(OutStreamer);
return; return;
} }
// Darwin call instructions are just normal call instructions with different // Darwin call instructions are just normal call instructions with different
// clobber semantics (they clobber R9). // clobber semantics (they clobber R9).
case ARM::BX_CALL: { case ARM::BX_CALL: {
MCInstBuilder(ARM::MOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR) .addReg(ARM::LR)
.addReg(ARM::PC) .addReg(ARM::PC)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::BX) OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()));
.emit(OutStreamer);
return; return;
} }
case ARM::tBX_CALL: { case ARM::tBX_CALL: {
MCInstBuilder(ARM::tMOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::LR) .addReg(ARM::LR)
.addReg(ARM::PC) .addReg(ARM::PC)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tBX) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::BMOVPCRX_CALL: { case ARM::BMOVPCRX_CALL: {
MCInstBuilder(ARM::MOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR) .addReg(ARM::LR)
.addReg(ARM::PC) .addReg(ARM::PC)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::MOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::PC) .addReg(ARM::PC)
.addImm(MI->getOperand(0).getReg()) .addImm(MI->getOperand(0).getReg())
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::BMOVPCB_CALL: { case ARM::BMOVPCB_CALL: {
MCInstBuilder(ARM::MOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR) .addReg(ARM::LR)
.addReg(ARM::PC) .addReg(ARM::PC)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
const GlobalValue *GV = MI->getOperand(0).getGlobal(); const GlobalValue *GV = MI->getOperand(0).getGlobal();
MCSymbol *GVSym = Mang->getSymbol(GV); MCSymbol *GVSym = Mang->getSymbol(GV);
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
MCInstBuilder(ARM::Bcc) OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
.addExpr(GVSymExpr) .addExpr(GVSymExpr)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::MOVi16_ga_pcrel: case ARM::MOVi16_ga_pcrel:
@ -1469,14 +1460,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutContext)); OutContext));
// Form and emit the add. // Form and emit the add.
MCInstBuilder(ARM::tADDhirr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC) .addReg(ARM::PC)
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::PICADD: { case ARM::PICADD: {
@ -1491,7 +1481,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutContext)); OutContext));
// Form and emit the add. // Form and emit the add.
MCInstBuilder(ARM::ADDrr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
@ -1499,8 +1489,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(MI->getOperand(3).getImm()) .addImm(MI->getOperand(3).getImm())
.addReg(MI->getOperand(4).getReg()) .addReg(MI->getOperand(4).getReg())
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::PICSTR: case ARM::PICSTR:
@ -1536,15 +1525,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
} }
MCInstBuilder(Opcode) OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addImm(0) .addImm(0)
// Add predicate operands. // Add predicate operands.
.addImm(MI->getOperand(3).getImm()) .addImm(MI->getOperand(3).getImm())
.addReg(MI->getOperand(4).getReg()) .addReg(MI->getOperand(4).getReg()));
.emit(OutStreamer);
return; return;
} }
@ -1574,13 +1562,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
case ARM::t2BR_JT: { case ARM::t2BR_JT: {
// Lower and emit the instruction itself, then the jump table following it. // Lower and emit the instruction itself, then the jump table following it.
MCInstBuilder(ARM::tMOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
// Output the data for the jump table itself // Output the data for the jump table itself
EmitJump2Table(MI); EmitJump2Table(MI);
@ -1588,13 +1575,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
case ARM::t2TBB_JT: { case ARM::t2TBB_JT: {
// Lower and emit the instruction itself, then the jump table following it. // Lower and emit the instruction itself, then the jump table following it.
MCInstBuilder(ARM::t2TBB) OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
// Output the data for the jump table itself // Output the data for the jump table itself
EmitJump2Table(MI); EmitJump2Table(MI);
@ -1604,13 +1590,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
case ARM::t2TBH_JT: { case ARM::t2TBH_JT: {
// Lower and emit the instruction itself, then the jump table following it. // Lower and emit the instruction itself, then the jump table following it.
MCInstBuilder(ARM::t2TBH) OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
// Add predicate operands. // Add predicate operands.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
// Output the data for the jump table itself // Output the data for the jump table itself
EmitJump2Table(MI); EmitJump2Table(MI);
@ -1671,7 +1656,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
case ARM::BR_JTadd: { case ARM::BR_JTadd: {
// Lower and emit the instruction itself, then the jump table following it. // Lower and emit the instruction itself, then the jump table following it.
// add pc, target, idx // add pc, target, idx
MCInstBuilder(ARM::ADDrr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
@ -1679,8 +1664,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// Add 's' bit operand (always reg0 for this) // Add 's' bit operand (always reg0 for this)
.addReg(0) .addReg(0));
.emit(OutStreamer);
// Output the data for the jump table itself // Output the data for the jump table itself
EmitJumpTable(MI); EmitJumpTable(MI);
@ -1725,15 +1709,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
unsigned ValReg = MI->getOperand(1).getReg(); unsigned ValReg = MI->getOperand(1).getReg();
MCSymbol *Label = GetARMSJLJEHLabel(); MCSymbol *Label = GetARMSJLJEHLabel();
OutStreamer.AddComment("eh_setjmp begin"); OutStreamer.AddComment("eh_setjmp begin");
MCInstBuilder(ARM::tMOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ValReg) .addReg(ValReg)
.addReg(ARM::PC) .addReg(ARM::PC)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tADDi3) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
.addReg(ValReg) .addReg(ValReg)
// 's' bit operand // 's' bit operand
.addReg(ARM::CPSR) .addReg(ARM::CPSR)
@ -1741,10 +1724,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(7) .addImm(7)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tSTRi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
.addReg(ValReg) .addReg(ValReg)
.addReg(SrcReg) .addReg(SrcReg)
// The offset immediate is #4. The operand value is scaled by 4 for the // The offset immediate is #4. The operand value is scaled by 4 for the
@ -1752,34 +1734,30 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(1) .addImm(1)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tMOVi8) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
.addReg(ARM::R0) .addReg(ARM::R0)
.addReg(ARM::CPSR) .addReg(ARM::CPSR)
.addImm(0) .addImm(0)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
MCInstBuilder(ARM::tB) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
.addExpr(SymbolExpr) .addExpr(SymbolExpr)
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
OutStreamer.AddComment("eh_setjmp end"); OutStreamer.AddComment("eh_setjmp end");
MCInstBuilder(ARM::tMOVi8) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
.addReg(ARM::R0) .addReg(ARM::R0)
.addReg(ARM::CPSR) .addReg(ARM::CPSR)
.addImm(1) .addImm(1)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
OutStreamer.EmitLabel(Label); OutStreamer.EmitLabel(Label);
return; return;
@ -1797,7 +1775,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
unsigned ValReg = MI->getOperand(1).getReg(); unsigned ValReg = MI->getOperand(1).getReg();
OutStreamer.AddComment("eh_setjmp begin"); OutStreamer.AddComment("eh_setjmp begin");
MCInstBuilder(ARM::ADDri) OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
.addReg(ValReg) .addReg(ValReg)
.addReg(ARM::PC) .addReg(ARM::PC)
.addImm(8) .addImm(8)
@ -1805,29 +1783,26 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// 's' bit operand (always reg0 for this). // 's' bit operand (always reg0 for this).
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::STRi12) OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
.addReg(ValReg) .addReg(ValReg)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(4) .addImm(4)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::MOVi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
.addReg(ARM::R0) .addReg(ARM::R0)
.addImm(0) .addImm(0)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// 's' bit operand (always reg0 for this). // 's' bit operand (always reg0 for this).
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::ADDri) OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
.addReg(ARM::PC) .addReg(ARM::PC)
.addReg(ARM::PC) .addReg(ARM::PC)
.addImm(0) .addImm(0)
@ -1835,19 +1810,17 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// 's' bit operand (always reg0 for this). // 's' bit operand (always reg0 for this).
.addReg(0) .addReg(0));
.emit(OutStreamer);
OutStreamer.AddComment("eh_setjmp end"); OutStreamer.AddComment("eh_setjmp end");
MCInstBuilder(ARM::MOVi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
.addReg(ARM::R0) .addReg(ARM::R0)
.addImm(1) .addImm(1)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0)
// 's' bit operand (always reg0 for this). // 's' bit operand (always reg0 for this).
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::Int_eh_sjlj_longjmp: { case ARM::Int_eh_sjlj_longjmp: {
@ -1857,39 +1830,35 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// bx $scratch // bx $scratch
unsigned SrcReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(0).getReg();
unsigned ScratchReg = MI->getOperand(1).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg();
MCInstBuilder(ARM::LDRi12) OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ARM::SP) .addReg(ARM::SP)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(8) .addImm(8)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::LDRi12) OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ScratchReg) .addReg(ScratchReg)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(4) .addImm(4)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::LDRi12) OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ARM::R7) .addReg(ARM::R7)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(0) .addImm(0)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::BX) OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
.addReg(ScratchReg) .addReg(ScratchReg)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
case ARM::tInt_eh_sjlj_longjmp: { case ARM::tInt_eh_sjlj_longjmp: {
@ -1900,7 +1869,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// bx $scratch // bx $scratch
unsigned SrcReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(0).getReg();
unsigned ScratchReg = MI->getOperand(1).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg();
MCInstBuilder(ARM::tLDRi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ScratchReg) .addReg(ScratchReg)
.addReg(SrcReg) .addReg(SrcReg)
// The offset immediate is #8. The operand value is scaled by 4 for the // The offset immediate is #8. The operand value is scaled by 4 for the
@ -1908,41 +1877,36 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(2) .addImm(2)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tMOVr) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::SP) .addReg(ARM::SP)
.addReg(ScratchReg) .addReg(ScratchReg)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tLDRi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ScratchReg) .addReg(ScratchReg)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(1) .addImm(1)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tLDRi) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ARM::R7) .addReg(ARM::R7)
.addReg(SrcReg) .addReg(SrcReg)
.addImm(0) .addImm(0)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
MCInstBuilder(ARM::tBX) OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
.addReg(ScratchReg) .addReg(ScratchReg)
// Predicate. // Predicate.
.addImm(ARMCC::AL) .addImm(ARMCC::AL)
.addReg(0) .addReg(0));
.emit(OutStreamer);
return; return;
} }
} }

44
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -350,11 +350,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCSymbol *PICBase = MF->getPICBaseSymbol(); MCSymbol *PICBase = MF->getPICBaseSymbol();
// Emit the 'bl'. // Emit the 'bl'.
MCInstBuilder(PPC::BL_Darwin) // Darwin vs SVR4 doesn't matter here. OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL_Darwin) // Darwin vs SVR4 doesn't matter here.
// FIXME: We would like an efficient form for this, so we don't have to do // FIXME: We would like an efficient form for this, so we don't have to do
// a lot of extra uniquing. // a lot of extra uniquing.
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)) .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
.emit(OutStreamer);
// Emit the label. // Emit the label.
OutStreamer.EmitLabel(PICBase); OutStreamer.EmitLabel(PICBase);
@ -403,9 +402,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Into: %R3 = MFCR ;; cr7 // Into: %R3 = MFCR ;; cr7
OutStreamer.AddComment(PPCInstPrinter:: OutStreamer.AddComment(PPCInstPrinter::
getRegisterName(MI->getOperand(1).getReg())); getRegisterName(MI->getOperand(1).getReg()));
MCInstBuilder(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR) OutStreamer.EmitInstruction(MCInstBuilder(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()));
.emit(OutStreamer);
return; return;
case PPC::SYNC: case PPC::SYNC:
// In Book E sync is called msync, handle this special case here... // In Book E sync is called msync, handle this special case here...
@ -586,36 +584,34 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol); OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol);
// mflr r0 // mflr r0
MCInstBuilder(PPC::MFLR).addReg(PPC::R0).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R0));
// FIXME: MCize this. // FIXME: MCize this.
OutStreamer.EmitRawText("\tbcl 20, 31, " + Twine(AnonSymbol->getName())); OutStreamer.EmitRawText("\tbcl 20, 31, " + Twine(AnonSymbol->getName()));
OutStreamer.EmitLabel(AnonSymbol); OutStreamer.EmitLabel(AnonSymbol);
// mflr r11 // mflr r11
MCInstBuilder(PPC::MFLR).addReg(PPC::R11).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R11));
// addis r11, r11, ha16(LazyPtr - AnonSymbol) // addis r11, r11, ha16(LazyPtr - AnonSymbol)
const MCExpr *Sub = const MCExpr *Sub =
MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(LazyPtr, OutContext), MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(LazyPtr, OutContext),
MCSymbolRefExpr::Create(AnonSymbol, OutContext), MCSymbolRefExpr::Create(AnonSymbol, OutContext),
OutContext); OutContext);
MCInstBuilder(PPC::ADDIS) OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS)
.addReg(PPC::R11) .addReg(PPC::R11)
.addReg(PPC::R11) .addReg(PPC::R11)
.addExpr(Sub) .addExpr(Sub));
.emit(OutStreamer);
// mtlr r0 // mtlr r0
MCInstBuilder(PPC::MTLR).addReg(PPC::R0).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTLR).addReg(PPC::R0));
// ldu r12, lo16(LazyPtr - AnonSymbol)(r11) // ldu r12, lo16(LazyPtr - AnonSymbol)(r11)
// lwzu r12, lo16(LazyPtr - AnonSymbol)(r11) // lwzu r12, lo16(LazyPtr - AnonSymbol)(r11)
MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
.addReg(PPC::R12) .addReg(PPC::R12)
.addExpr(Sub).addExpr(Sub) .addExpr(Sub).addExpr(Sub)
.addReg(PPC::R11) .addReg(PPC::R11));
.emit(OutStreamer);
// mtctr r12 // mtctr r12
MCInstBuilder(PPC::MTCTR).addReg(PPC::R12).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
// bctr // bctr
MCInstBuilder(PPC::BCTR).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR));
OutStreamer.SwitchSection(LSPSection); OutStreamer.SwitchSection(LSPSection);
OutStreamer.EmitLabel(LazyPtr); OutStreamer.EmitLabel(LazyPtr);
@ -653,26 +649,24 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
const MCExpr *LazyPtrHa16 = const MCExpr *LazyPtrHa16 =
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_HA16, MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_HA16,
OutContext); OutContext);
MCInstBuilder(PPC::LIS) OutStreamer.EmitInstruction(MCInstBuilder(PPC::LIS)
.addReg(PPC::R11) .addReg(PPC::R11)
.addExpr(LazyPtrHa16) .addExpr(LazyPtrHa16));
.emit(OutStreamer);
const MCExpr *LazyPtrLo16 = const MCExpr *LazyPtrLo16 =
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_LO16, MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_LO16,
OutContext); OutContext);
// ldu r12, lo16(LazyPtr)(r11) // ldu r12, lo16(LazyPtr)(r11)
// lwzu r12, lo16(LazyPtr)(r11) // lwzu r12, lo16(LazyPtr)(r11)
MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU) OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
.addReg(PPC::R12) .addReg(PPC::R12)
.addExpr(LazyPtrLo16).addExpr(LazyPtrLo16) .addExpr(LazyPtrLo16).addExpr(LazyPtrLo16)
.addReg(PPC::R11) .addReg(PPC::R11));
.emit(OutStreamer);
// mtctr r12 // mtctr r12
MCInstBuilder(PPC::MTCTR).addReg(PPC::R12).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
// bctr // bctr
MCInstBuilder(PPC::BCTR).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR));
OutStreamer.SwitchSection(LSPSection); OutStreamer.SwitchSection(LSPSection);
OutStreamer.EmitLabel(LazyPtr); OutStreamer.EmitLabel(LazyPtr);

31
lib/Target/X86/X86MCInstLower.cpp
View File

@ -555,7 +555,7 @@ ReSimplify:
OutMI.addOperand(MCOperand::CreateReg(X86::R10)); OutMI.addOperand(MCOperand::CreateReg(X86::R10));
OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
MCInstBuilder(X86::RET).emit(AsmPrinter.OutStreamer); AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
break; break;
} }
} }
@ -572,7 +572,7 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
MCContext &context = OutStreamer.getContext(); MCContext &context = OutStreamer.getContext();
if (needsPadding) if (needsPadding)
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
MCSymbolRefExpr::VariantKind SRVK; MCSymbolRefExpr::VariantKind SRVK;
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
@ -622,9 +622,9 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
OutStreamer.EmitInstruction(LEA); OutStreamer.EmitInstruction(LEA);
if (needsPadding) { if (needsPadding) {
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
MCInstBuilder(X86::REX64_PREFIX).emit(OutStreamer); OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
} }
StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
@ -634,9 +634,9 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
MCSymbolRefExpr::VK_PLT, MCSymbolRefExpr::VK_PLT,
context); context);
MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
.addExpr(tlsRef) : X86::CALLpcrel32)
.emit(OutStreamer); .addExpr(tlsRef));
} }
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
@ -690,17 +690,15 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCSymbol *PICBase = MF->getPICBaseSymbol(); MCSymbol *PICBase = MF->getPICBaseSymbol();
// FIXME: We would like an efficient form for this, so we don't have to do a // FIXME: We would like an efficient form for this, so we don't have to do a
// lot of extra uniquing. // lot of extra uniquing.
MCInstBuilder(X86::CALLpcrel32) OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)) .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
.emit(OutStreamer);
// Emit the label. // Emit the label.
OutStreamer.EmitLabel(PICBase); OutStreamer.EmitLabel(PICBase);
// popl $reg // popl $reg
MCInstBuilder(X86::POP32r) OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()));
.emit(OutStreamer);
return; return;
} }
@ -730,11 +728,10 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
DotExpr, OutContext); DotExpr, OutContext);
MCInstBuilder(X86::ADD32ri) OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
.addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addExpr(DotExpr) .addExpr(DotExpr));
.emit(OutStreamer);
return; return;
} }
} }