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Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

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It introduced two regressions on 64-bit big-endian targets running under N32
(MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets
comparisons such as BEQ compare the whole GPR64 but incorrectly tell the
instruction selector that they operate on GPR32's. This leads to the
elimination of i32->i64 extensions that are actually required by
comparisons to work correctly.

There's currently a patch under review that fixes this problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris 2015-08-04 14:26:35 +00:00
parent 7f68d74dde
commit edcaae782e
5 changed files with 15 additions and 11 deletions
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8
lib/Target/Mips/Mips64InstrInfo.td
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@ -500,14 +500,6 @@ def : MipsPat<(trunc (assertzext GPR64:$src)),
def : MipsPat<(i32 (trunc GPR64:$src)),
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
// Bypass trunc nodes for bitwise ops.
def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
// variable shift instructions patterns
def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
(DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;

2
test/CodeGen/Mips/delay-slot-kill.ll
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@ -1,4 +1,6 @@
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
; We have to XFAIL this temporarily because of the reversion of r229675.
; XFAIL: *
; Currently, the following IR assembly generates a KILL instruction between
; the bitwise-and instruction and the return instruction. We verify that the

5
test/CodeGen/Mips/llvm-ir/and.ll
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@ -59,7 +59,10 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: and_i32:
; ALL: and $2, $4, $5
; GP32: and $2, $4, $5
; GP64: and $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
%r = and i32 %a, %b
ret i32 %r

6
test/CodeGen/Mips/llvm-ir/or.ll
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@ -59,7 +59,11 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: or_i32:
; ALL: or $2, $4, $5
; GP32: or $2, $4, $5
; GP64: or $[[T0:[0-9]+]], $4, $5
; FIXME: The sll instruction below is redundant.
; GP64: sll $2, $[[T0]], 0
%r = or i32 %a, %b
ret i32 %r

5
test/CodeGen/Mips/llvm-ir/xor.ll
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@ -59,7 +59,10 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: xor_i32:
; ALL: xor $2, $4, $5
; GP32: xor $2, $4, $5
; GP64: xor $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
%r = xor i32 %a, %b
ret i32 %r