From ee339f4b2ab3e7789f02a714bbd8b1fb9f956467 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 27 Jan 2008 23:21:58 +0000 Subject: [PATCH] fix a crash on CodeGen/X86/vector-rem.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46422 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 2c2f5e95b06..5d1f70f2eb7 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1306,10 +1306,12 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) { return DAG.getNode(ISD::SREM, VT, N0, N1); // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 - uint64_t SignBit = MVT::getIntVTSignBit(VT); - if (DAG.MaskedValueIsZero(N1, SignBit) && - DAG.MaskedValueIsZero(N0, SignBit)) - return DAG.getNode(ISD::UREM, VT, N0, N1); + if (!MVT::isVector(VT)) { + uint64_t SignBit = MVT::getIntVTSignBit(VT); + if (DAG.MaskedValueIsZero(N1, SignBit) && + DAG.MaskedValueIsZero(N0, SignBit)) + return DAG.getNode(ISD::UREM, VT, N0, N1); + } // If X/C can be simplified by the division-by-constant logic, lower // X%C to the equivalent of X-X/C*C.