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Use the correct register class for load instructions - fixes

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compilation of MultiSource/Benchmarks/Bullet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-10-07 05:50:44 +00:00
parent 5d18d92aad
commit ee56ea6243
1 changed files with 8 additions and 1 deletions
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9
lib/Target/ARM/ARMFastISel.cpp
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@ -652,33 +652,40 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
assert(VT.isSimple() && "Non-simple types are invalid here!");
unsigned Opc;
TargetRegisterClass *RC;
bool isFloat = false;
switch (VT.getSimpleVT().SimpleTy) {
default:
// This is mostly going to be Neon/vector support.
return false;
// Using thumb1 instructions for now, use the appropriate RC.
case MVT::i16:
Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
VT = MVT::i32;
break;
case MVT::i8:
Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
VT = MVT::i32;
break;
case MVT::i32:
Opc = isThumb ? ARM::tLDR : ARM::LDR;
RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
break;
case MVT::f32:
Opc = ARM::VLDRS;
RC = TLI.getRegClassFor(VT);
isFloat = true;
break;
case MVT::f64:
Opc = ARM::VLDRD;
RC = TLI.getRegClassFor(VT);
isFloat = true;
break;
}
ResultReg = createResultReg(TLI.getRegClassFor(VT));
ResultReg = createResultReg(RC);
// TODO: Fix the Addressing modes so that these can share some code.
// Since this is a Thumb1 load this will work in Thumb1 or 2 mode.