mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-28 22:20:43 +00:00
Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3f4f34c7ba
commit
eea723fe02
@ -1946,71 +1946,11 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v2di :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v2di">,
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v4si :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v4si">,
|
||||
Intrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v8hi :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v8hi">,
|
||||
Intrinsic<[llvm_v8i16_ty],
|
||||
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v16qi :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v16qi">,
|
||||
Intrinsic<[llvm_v16i8_ty],
|
||||
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v2df :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v2df">,
|
||||
Intrinsic<[llvm_v2f64_ty],
|
||||
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v4sf :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v4sf">,
|
||||
Intrinsic<[llvm_v4f32_ty],
|
||||
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_256">,
|
||||
Intrinsic<[llvm_v4i64_ty],
|
||||
[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v4di_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v4di256">,
|
||||
Intrinsic<[llvm_v4i64_ty],
|
||||
[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v8si_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v8si256">,
|
||||
Intrinsic<[llvm_v8i32_ty],
|
||||
[llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v16hi_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v16hi256">,
|
||||
Intrinsic<[llvm_v16i16_ty],
|
||||
[llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v32qi_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v32qi256">,
|
||||
Intrinsic<[llvm_v32i8_ty],
|
||||
[llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v4df_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v4df256">,
|
||||
Intrinsic<[llvm_v4f64_ty],
|
||||
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcmov_v8sf_256 :
|
||||
GCCBuiltin<"__builtin_ia32_vpcmov_v8sf256">,
|
||||
Intrinsic<[llvm_v8f32_ty],
|
||||
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
|
||||
[IntrNoMem]>;
|
||||
def int_x86_xop_vpcomeqb :
|
||||
GCCBuiltin<"__builtin_ia32_vpcomeqb">,
|
||||
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
|
||||
|
||||
@ -305,128 +305,3 @@ defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
|
||||
defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
|
||||
int_x86_xop_vpermil2ps_256, memopv4f32, memopv8f32>;
|
||||
|
||||
// XOP Intrinsics patterns
|
||||
|
||||
let Predicates = [HasXOP] in {
|
||||
// VPCMOV di
|
||||
def : Pat<(int_x86_xop_vpcmov_v2di VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v2di VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v2di VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4di_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4di_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4di_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VPCMOV si
|
||||
def : Pat<(int_x86_xop_vpcmov_v4si VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4si VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4si VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8si_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8si_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8si_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
|
||||
// VPCMOV hi
|
||||
def : Pat<(int_x86_xop_vpcmov_v8hi VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8hi VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8hi VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v16hi_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v16hi_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v16hi_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VPCMOV qi
|
||||
def : Pat<(int_x86_xop_vpcmov_v16qi VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v16qi VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v16qi VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v32qi_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v32qi_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v32qi_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VPCMOV df
|
||||
def : Pat<(int_x86_xop_vpcmov_v2df VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v2df VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v2df VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4df_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4df_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4df_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VPCMOV sf
|
||||
def : Pat<(int_x86_xop_vpcmov_v4sf VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VPCMOVrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4sf VR128:$src1, VR128:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v4sf VR128:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR128:$src3),
|
||||
(VPCMOVmr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8sf_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VPCMOVrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8sf_256 VR256:$src1, VR256:$src2,
|
||||
(bitconvert (memopv2i64 addr:$src3))),
|
||||
(VPCMOVrmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_xop_vpcmov_v8sf_256 VR256:$src1,
|
||||
(bitconvert (memopv2i64 addr:$src2)),
|
||||
VR256:$src3),
|
||||
(VPCMOVmrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
} // let Predicates = [HasXOP]
|
||||
|
||||
|
||||
@ -67,48 +67,6 @@ define <2 x i64> @test_int_x86_xop_vpcmov(<2 x i64> %a0, <2 x i64> %a1, <2 x i64
|
||||
}
|
||||
declare <2 x i64> @llvm.x86.xop.vpcmov(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
define <2 x i64> @test_int_x86_xop_vpcmov_v2di(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <2 x i64> @llvm.x86.xop.vpcmov.v2di(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) ;
|
||||
ret <2 x i64> %res
|
||||
}
|
||||
declare <2 x i64> @llvm.x86.xop.vpcmov.v2di(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
|
||||
|
||||
define <4 x i32> @test_int_x86_xop_vpcmov_v4si(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <4 x i32> @llvm.x86.xop.vpcmov.v4si(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) ;
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
declare <4 x i32> @llvm.x86.xop.vpcmov.v4si(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
define <8 x i16> @test_int_x86_xop_vpcmov_v8hi(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <8 x i16> @llvm.x86.xop.vpcmov.v8hi(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2) ;
|
||||
ret <8 x i16> %res
|
||||
}
|
||||
declare <8 x i16> @llvm.x86.xop.vpcmov.v8hi(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
|
||||
|
||||
define <16 x i8> @test_int_x86_xop_vpcmov_v16qi(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <16 x i8> @llvm.x86.xop.vpcmov.v16qi(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ;
|
||||
ret <16 x i8> %res
|
||||
}
|
||||
declare <16 x i8> @llvm.x86.xop.vpcmov.v16qi(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
|
||||
|
||||
define <2 x double> @test_int_x86_xop_vpcmov_v2df(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <2 x double> @llvm.x86.xop.vpcmov.v2df(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ;
|
||||
ret <2 x double> %res
|
||||
}
|
||||
declare <2 x double> @llvm.x86.xop.vpcmov.v2df(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
|
||||
|
||||
define <4 x float> @test_int_x86_xop_vpcmov_v4sf(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
|
||||
; CHECK: vpcmov
|
||||
%res = call <4 x float> @llvm.x86.xop.vpcmov.v4sf(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ;
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.xop.vpcmov.v4sf(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
|
||||
|
||||
define <4 x i64> @test_int_x86_xop_vpcmov_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
@ -133,54 +91,6 @@ define <4 x i64> @test_int_x86_xop_vpcmov_256_rm(<4 x i64> %a0, <4 x i64> %a1, <
|
||||
}
|
||||
declare <4 x i64> @llvm.x86.xop.vpcmov.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
|
||||
|
||||
define <4 x i64> @test_int_x86_xop_vpcmov_v4di_256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <4 x i64> @llvm.x86.xop.vpcmov.v4di.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) ;
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
declare <4 x i64> @llvm.x86.xop.vpcmov.v4di.256(<4 x i64>, <4 x i64>, <4 x i64>) nounwind readnone
|
||||
|
||||
define <8 x i32> @test_int_x86_xop_vpcmov_v8si_256(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <8 x i32> @llvm.x86.xop.vpcmov.v8si.256(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2) ;
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
declare <8 x i32> @llvm.x86.xop.vpcmov.v8si.256(<8 x i32>, <8 x i32>, <8 x i32>) nounwind readnone
|
||||
|
||||
define <16 x i16> @test_int_x86_xop_vpcmov_v16hi_256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <16 x i16> @llvm.x86.xop.vpcmov.v16hi.256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2) ;
|
||||
ret <16 x i16> %res
|
||||
}
|
||||
declare <16 x i16> @llvm.x86.xop.vpcmov.v16hi.256(<16 x i16>, <16 x i16>, <16 x i16>) nounwind readnone
|
||||
|
||||
define <32 x i8> @test_int_x86_xop_vpcmov_v32qi_256(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <32 x i8> @llvm.x86.xop.vpcmov.v32qi.256(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ;
|
||||
ret <32 x i8> %res
|
||||
}
|
||||
declare <32 x i8> @llvm.x86.xop.vpcmov.v32qi.256(<32 x i8>, <32 x i8>, <32 x i8>) nounwind readnone
|
||||
|
||||
define <4 x double> @test_int_x86_xop_vpcmov_v4df_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <4 x double> @llvm.x86.xop.vpcmov.v4df.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ;
|
||||
ret <4 x double> %res
|
||||
}
|
||||
declare <4 x double> @llvm.x86.xop.vpcmov.v4df.256(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
|
||||
|
||||
define <8 x float> @test_int_x86_xop_vpcmov_v8sf_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
|
||||
; CHECK: vpcmov
|
||||
; CHECK: ymm
|
||||
%res = call <8 x float> @llvm.x86.xop.vpcmov.v8sf.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ;
|
||||
ret <8 x float> %res
|
||||
}
|
||||
declare <8 x float> @llvm.x86.xop.vpcmov.v8sf.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
|
||||
|
||||
define <16 x i8> @test_int_x86_xop_vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
; CHECK:vpcomb
|
||||
%res = call <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8> %a0, <16 x i8> %a1) ;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user