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Refactor isThumb1Only() && isMClass() into a predicate called isV6M()
This must be enforced for all v6M cores, not just the cortex-m0, irregardless of the user-specified alignment. Patch by Charlie Turner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219300 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -310,15 +310,14 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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(hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
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isTargetNetBSD())) ||
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(hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
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// The one exception is cortex-m0, which despite being v6, does not
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// support unaligned accesses. Rather than make the above boolean
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// expression even more obtuse, just override the value here.
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if (isThumb1Only() && isMClass())
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AllowsUnalignedMem = false;
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} else {
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AllowsUnalignedMem = !(Align == StrictAlign);
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}
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// No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
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if (isV6M())
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AllowsUnalignedMem = false;
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switch (IT) {
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case DefaultIT:
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RestrictIT = hasV8Ops() ? true : false;
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@ -405,6 +405,10 @@ public:
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bool isRClass() const { return ARMProcClass == RClass; }
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bool isAClass() const { return ARMProcClass == AClass; }
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bool isV6M() const {
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return isThumb1Only() && isMClass();
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}
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bool isR9Reserved() const { return IsR9Reserved; }
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bool useMovt(const MachineFunction &MF) const;
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