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Teach legalize to promote copy(from|to)reg, instead of making the isel pass

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do it.  This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-18 17:54:55 +00:00
parent b422aeac9e
commit ef5cd1d3cf
2 changed files with 13 additions and 26 deletions
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17
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -380,7 +380,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
break; break;
case Expand: { case Promote:
Tmp2 = PromoteOp(Node->getOperand(1));
Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
break;
case Expand:
SDOperand Lo, Hi; SDOperand Lo, Hi;
ExpandOp(Node->getOperand(1), Lo, Hi); ExpandOp(Node->getOperand(1), Lo, Hi);
unsigned Reg = cast<RegSDNode>(Node)->getReg(); unsigned Reg = cast<RegSDNode>(Node)->getReg();
@ -390,10 +394,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
"Cannot expand multiple times yet (i64 -> i16)"); "Cannot expand multiple times yet (i64 -> i16)");
break; break;
} }
case Promote:
assert(0 && "CopyToReg should not require promotion!");
abort();
}
break; break;
case ISD::RET: case ISD::RET:
@ -917,6 +917,13 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
break; break;
case ISD::CopyFromReg:
Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
Node->getOperand(0));
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
break;
case ISD::SETCC: case ISD::SETCC:
assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
"SetCC type is not legal??"); "SetCC type is not legal??");

22
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -292,19 +292,7 @@ public:
FuncInfo.ValueMap.find(V); FuncInfo.ValueMap.find(V);
assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
MVT::ValueType RegVT = VT; return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
if (TLI.getTypeAction(VT) == 1) // Must promote this value?
RegVT = TLI.getTypeToTransformTo(VT);
N = DAG.getCopyFromReg(VMI->second, RegVT, DAG.getEntryNode());
if (RegVT != VT)
if (MVT::isFloatingPoint(VT))
N = DAG.getNode(ISD::FP_ROUND, VT, N);
else
N = DAG.getNode(ISD::TRUNCATE, VT, N);
return N;
} }
const SDOperand &setValue(const Value *V, SDOperand NewN) { const SDOperand &setValue(const Value *V, SDOperand NewN) {
@ -843,14 +831,6 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
assert((Op.getOpcode() != ISD::CopyFromReg || assert((Op.getOpcode() != ISD::CopyFromReg ||
cast<RegSDNode>(Op)->getReg() != Reg) && cast<RegSDNode>(Op)->getReg() != Reg) &&
"Copy from a reg to the same reg!"); "Copy from a reg to the same reg!");
MVT::ValueType VT = Op.getValueType();
if (TLI.getTypeAction(VT) == 1) { // Must promote this value?
if (MVT::isFloatingPoint(VT))
Op = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(VT), Op);
else
Op = DAG.getNode(ISD::ZERO_EXTEND, TLI.getTypeToTransformTo(VT), Op);
}
return DAG.getCopyToReg(SDL.getRoot(), Op, Reg); return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
} }