RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-13 14:47:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Track allocatable instead of reserved regs, and never take an unallocatable hint.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103828 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-05-14 22:02:56 +00:00
parent 8b3a8f5773
commit efa155fd6e
1 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/CodeGen/RegAllocFast.cpp
View File

@ -108,8 +108,8 @@ namespace {
// instruction, and so cannot be allocated. // instruction, and so cannot be allocated.
BitVector UsedInInstr; BitVector UsedInInstr;
// ReservedRegs - vector of reserved physical registers. // Allocatable - vector of allocatable physical registers.
BitVector ReservedRegs; BitVector Allocatable;
// atEndOfBlock - This flag is set after allocating all instructions in a // atEndOfBlock - This flag is set after allocating all instructions in a
// block, before emitting final spills. When it is set, LiveRegMap is no // block, before emitting final spills. When it is set, LiveRegMap is no
@ -394,7 +394,8 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
// Ignore invalid hints. // Ignore invalid hints.
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
!RC->contains(Hint) || UsedInInstr.test(Hint))) !RC->contains(Hint) || UsedInInstr.test(Hint)) ||
!Allocatable.test(Hint))
Hint = 0; Hint = 0;
// If there is no hint, peek at the first use of this register. // If there is no hint, peek at the first use of this register.
@ -404,7 +405,8 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
// Copy to physreg -> use physreg as hint. // Copy to physreg -> use physreg as hint.
if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) && if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) && SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
RC->contains(DstReg) && !UsedInInstr.test(DstReg)) { RC->contains(DstReg) && !UsedInInstr.test(DstReg) &&
Allocatable.test(DstReg)) {
Hint = DstReg; Hint = DstReg;
DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI); DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
} }
@ -413,7 +415,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
// Take hint when possible. // Take hint when possible.
if (Hint) { if (Hint) {
assert(RC->contains(Hint) && !UsedInInstr.test(Hint) && assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
"Invalid hint should have been cleared"); Allocatable.test(Hint) && "Invalid hint should have been cleared");
switch(PhysRegState[Hint]) { switch(PhysRegState[Hint]) {
case regDisabled: case regDisabled:
case regReserved: case regReserved:
@ -674,7 +676,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
VirtOpEnd = i+1; VirtOpEnd = i+1;
continue; continue;
} }
if (ReservedRegs.test(Reg)) continue; if (!Allocatable.test(Reg)) continue;
if (MO.isUse()) { if (MO.isUse()) {
usePhysReg(MO); usePhysReg(MO);
} else if (MO.isEarlyClobber()) { } else if (MO.isEarlyClobber()) {
@ -729,7 +731,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (ReservedRegs.test(Reg)) continue; if (!Allocatable.test(Reg)) continue;
definePhysReg(MBB, MI, Reg, (MO.isImplicit() || MO.isDead()) ? definePhysReg(MBB, MI, Reg, (MO.isImplicit() || MO.isDead()) ?
regFree : regReserved); regFree : regReserved);
continue; continue;
@ -797,7 +799,7 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
TII = TM->getInstrInfo(); TII = TM->getInstrInfo();
UsedInInstr.resize(TRI->getNumRegs()); UsedInInstr.resize(TRI->getNumRegs());
ReservedRegs = TRI->getReservedRegs(*MF); Allocatable = TRI->getAllocatableSet(*MF);
// initialize the virtual->physical register map to have a 'null' // initialize the virtual->physical register map to have a 'null'
// mapping for all virtual registers // mapping for all virtual registers