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Name this variable to be what it really is!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-30 01:58:51 +00:00
parent 55334fc45c
commit f155635b53
1 changed files with 4 additions and 4 deletions
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8
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -205,13 +205,13 @@ unsigned SimpleSched::Emit(SDOperand Op) {
Emit(Op.getOperand(i)); Emit(Op.getOperand(i));
break; break;
case ISD::CopyToReg: { case ISD::CopyToReg: {
SDOperand ChainOp; SDOperand FlagOp;
if (Op.getNumOperands() == 4) if (Op.getNumOperands() == 4)
ChainOp = Op.getOperand(3); FlagOp = Op.getOperand(3);
if (Op.getOperand(0).Val != ChainOp.Val) if (Op.getOperand(0).Val != FlagOp.Val)
Emit(Op.getOperand(0)); // Emit the chain. Emit(Op.getOperand(0)); // Emit the chain.
unsigned Val = Emit(Op.getOperand(2)); unsigned Val = Emit(Op.getOperand(2));
if (ChainOp.Val) Emit(ChainOp); if (FlagOp.Val) Emit(FlagOp);
MRI.copyRegToReg(*BB, BB->end(), MRI.copyRegToReg(*BB, BB->end(),
cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val, cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
RegMap->getRegClass(Val)); RegMap->getRegClass(Val));