mirror of
https://github.com/RPCS3/llvm.git
synced 2025-01-27 05:32:22 +00:00
AArch64 ILP32 relocations for assembly and ELF
Summary:
Add relocations for AArch64 ILP32. Includes:
- Addition of definitions for R_AARCH32_*
- Definition of new -target-abi: ilp32
- Definition of data layout string
- Tests for added relocations. Not comprehensive, but matches
existing tests for 64-bit. Renames "CHECK-OBJ" to "CHECK-OBJ-LP64".
- Tests for llvm-readobj
Reviewers: zatrazz, peter.smith, echristo, t.p.northover
Subscribers: aemerson, rengolin, mehdi_amini
Differential Revision: https://reviews.llvm.org/D25159
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284973 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joel Jones
parent
1c01a24b73
commit
f2152944cb
@ -3,145 +3,199 @@
|
||||
#error "ELF_RELOC must be defined"
|
||||
#endif
|
||||
|
||||
// ABI release 1.0
|
||||
ELF_RELOC(R_AARCH64_NONE, 0)
|
||||
// Based on ABI release 1.1-beta, dated 6 November 2013. NB: The cover page of
|
||||
// this document, IHI0056C_beta_aaelf64.pdf, on infocenter.arm.com, still
|
||||
// labels this as release 1.0.
|
||||
ELF_RELOC(R_AARCH64_NONE, 0)
|
||||
ELF_RELOC(R_AARCH64_ABS64, 0x101)
|
||||
ELF_RELOC(R_AARCH64_ABS32, 0x102)
|
||||
ELF_RELOC(R_AARCH64_ABS16, 0x103)
|
||||
ELF_RELOC(R_AARCH64_PREL64, 0x104)
|
||||
ELF_RELOC(R_AARCH64_PREL32, 0x105)
|
||||
ELF_RELOC(R_AARCH64_PREL16, 0x106)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G0, 0x107)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G0_NC, 0x108)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G1, 0x109)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G1_NC, 0x10a)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G2, 0x10b)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G2_NC, 0x10c)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G3, 0x10d)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G0, 0x10e)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G1, 0x10f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G2, 0x110)
|
||||
ELF_RELOC(R_AARCH64_LD_PREL_LO19, 0x111)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_LO21, 0x112)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_PG_HI21, 0x113)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_PG_HI21_NC, 0x114)
|
||||
ELF_RELOC(R_AARCH64_ADD_ABS_LO12_NC, 0x115)
|
||||
ELF_RELOC(R_AARCH64_LDST8_ABS_LO12_NC, 0x116)
|
||||
ELF_RELOC(R_AARCH64_TSTBR14, 0x117)
|
||||
ELF_RELOC(R_AARCH64_CONDBR19, 0x118)
|
||||
ELF_RELOC(R_AARCH64_JUMP26, 0x11a)
|
||||
ELF_RELOC(R_AARCH64_CALL26, 0x11b)
|
||||
ELF_RELOC(R_AARCH64_LDST16_ABS_LO12_NC, 0x11c)
|
||||
ELF_RELOC(R_AARCH64_LDST32_ABS_LO12_NC, 0x11d)
|
||||
ELF_RELOC(R_AARCH64_LDST64_ABS_LO12_NC, 0x11e)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G0, 0x11f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G0_NC, 0x120)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G1, 0x121)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G1_NC, 0x122)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G2, 0x123)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G2_NC, 0x124)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G3, 0x125)
|
||||
ELF_RELOC(R_AARCH64_LDST128_ABS_LO12_NC, 0x12b)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G0, 0x12c)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G0_NC, 0x12d)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G1, 0x12e)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G1_NC, 0x12f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G2, 0x130)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G2_NC, 0x131)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G3, 0x132)
|
||||
ELF_RELOC(R_AARCH64_GOTREL64, 0x133)
|
||||
ELF_RELOC(R_AARCH64_GOTREL32, 0x134)
|
||||
ELF_RELOC(R_AARCH64_GOT_LD_PREL19, 0x135)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOTOFF_LO15, 0x136)
|
||||
ELF_RELOC(R_AARCH64_ADR_GOT_PAGE, 0x137)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOT_LO12_NC, 0x138)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOTPAGE_LO15, 0x139)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADR_PREL21, 0x200)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADR_PAGE21, 0x201)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADD_LO12_NC, 0x202)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_MOVW_G1, 0x203)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_MOVW_G0_NC, 0x204)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADR_PREL21, 0x205)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADR_PAGE21, 0x206)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_LO12_NC, 0x207)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_G1, 0x208)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_G0_NC, 0x209)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LD_PREL19, 0x20a)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G2, 0x20b)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G1, 0x20c)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, 0x20d)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G0, 0x20e)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, 0x20f)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_HI12, 0x210)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_LO12, 0x211)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC, 0x212)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST8_DTPREL_LO12, 0x213)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, 0x214)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST16_DTPREL_LO12, 0x215)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, 0x216)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST32_DTPREL_LO12, 0x217)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, 0x218)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST64_DTPREL_LO12, 0x219)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, 0x21a)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 0x21b)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 0x21c)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 0x21d)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 0x21e)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 0x21f)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G2, 0x220)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G1, 0x221)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 0x222)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G0, 0x223)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 0x224)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_HI12, 0x225)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_LO12, 0x226)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 0x227)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST8_TPREL_LO12, 0x228)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC, 0x229)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST16_TPREL_LO12, 0x22a)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC, 0x22b)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12, 0x22c)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC, 0x22d)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12, 0x22e)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC, 0x22f)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19, 0x230)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21, 0x231)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21, 0x232)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC, 0x233)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC, 0x234)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1, 0x235)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC, 0x236)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LDR, 0x237)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADD, 0x238)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_CALL, 0x239)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12, 0x23a)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC, 0x23b)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12, 0x23c)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC, 0x23d)
|
||||
ELF_RELOC(R_AARCH64_COPY, 0x400)
|
||||
ELF_RELOC(R_AARCH64_GLOB_DAT, 0x401)
|
||||
ELF_RELOC(R_AARCH64_JUMP_SLOT, 0x402)
|
||||
ELF_RELOC(R_AARCH64_RELATIVE, 0x403)
|
||||
ELF_RELOC(R_AARCH64_TLS_DTPREL64, 0x404)
|
||||
ELF_RELOC(R_AARCH64_TLS_DTPMOD64, 0x405)
|
||||
ELF_RELOC(R_AARCH64_TLS_TPREL64, 0x406)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC, 0x407)
|
||||
ELF_RELOC(R_AARCH64_IRELATIVE, 0x408)
|
||||
|
||||
ELF_RELOC(R_AARCH64_ABS64, 0x101)
|
||||
ELF_RELOC(R_AARCH64_ABS32, 0x102)
|
||||
ELF_RELOC(R_AARCH64_ABS16, 0x103)
|
||||
ELF_RELOC(R_AARCH64_PREL64, 0x104)
|
||||
ELF_RELOC(R_AARCH64_PREL32, 0x105)
|
||||
ELF_RELOC(R_AARCH64_PREL16, 0x106)
|
||||
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G0, 0x107)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G0_NC, 0x108)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G1, 0x109)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G1_NC, 0x10a)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G2, 0x10b)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G2_NC, 0x10c)
|
||||
ELF_RELOC(R_AARCH64_MOVW_UABS_G3, 0x10d)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G0, 0x10e)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G1, 0x10f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_SABS_G2, 0x110)
|
||||
|
||||
ELF_RELOC(R_AARCH64_LD_PREL_LO19, 0x111)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_LO21, 0x112)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_PG_HI21, 0x113)
|
||||
ELF_RELOC(R_AARCH64_ADR_PREL_PG_HI21_NC, 0x114)
|
||||
ELF_RELOC(R_AARCH64_ADD_ABS_LO12_NC, 0x115)
|
||||
ELF_RELOC(R_AARCH64_LDST8_ABS_LO12_NC, 0x116)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TSTBR14, 0x117)
|
||||
ELF_RELOC(R_AARCH64_CONDBR19, 0x118)
|
||||
ELF_RELOC(R_AARCH64_JUMP26, 0x11a)
|
||||
ELF_RELOC(R_AARCH64_CALL26, 0x11b)
|
||||
|
||||
ELF_RELOC(R_AARCH64_LDST16_ABS_LO12_NC, 0x11c)
|
||||
ELF_RELOC(R_AARCH64_LDST32_ABS_LO12_NC, 0x11d)
|
||||
ELF_RELOC(R_AARCH64_LDST64_ABS_LO12_NC, 0x11e)
|
||||
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G0, 0x11f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G0_NC, 0x120)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G1, 0x121)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G1_NC, 0x122)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G2, 0x123)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G2_NC, 0x124)
|
||||
ELF_RELOC(R_AARCH64_MOVW_PREL_G3, 0x125)
|
||||
|
||||
ELF_RELOC(R_AARCH64_LDST128_ABS_LO12_NC, 0x12b)
|
||||
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G0, 0x12c)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G0_NC, 0x12d)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G1, 0x12e)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G1_NC, 0x12f)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G2, 0x130)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G2_NC, 0x131)
|
||||
ELF_RELOC(R_AARCH64_MOVW_GOTOFF_G3, 0x132)
|
||||
|
||||
ELF_RELOC(R_AARCH64_GOTREL64, 0x133)
|
||||
ELF_RELOC(R_AARCH64_GOTREL32, 0x134)
|
||||
|
||||
ELF_RELOC(R_AARCH64_GOT_LD_PREL19, 0x135)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOTOFF_LO15, 0x136)
|
||||
ELF_RELOC(R_AARCH64_ADR_GOT_PAGE, 0x137)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOT_LO12_NC, 0x138)
|
||||
ELF_RELOC(R_AARCH64_LD64_GOTPAGE_LO15, 0x139)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADR_PREL21, 0x200)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADR_PAGE21, 0x201)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_ADD_LO12_NC, 0x202)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_MOVW_G1, 0x203)
|
||||
ELF_RELOC(R_AARCH64_TLSGD_MOVW_G0_NC, 0x204)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADR_PREL21, 0x205)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADR_PAGE21, 0x206)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_LO12_NC, 0x207)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_G1, 0x208)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_G0_NC, 0x209)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LD_PREL19, 0x20a)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G2, 0x20b)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G1, 0x20c)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, 0x20d)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G0, 0x20e)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, 0x20f)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_HI12, 0x210)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_LO12, 0x211)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC, 0x212)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST8_DTPREL_LO12, 0x213)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC, 0x214)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST16_DTPREL_LO12, 0x215)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, 0x216)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST32_DTPREL_LO12, 0x217)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, 0x218)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST64_DTPREL_LO12, 0x219)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, 0x21a)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 0x21b)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 0x21c)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 0x21d)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 0x21e)
|
||||
ELF_RELOC(R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 0x21f)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G2, 0x220)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G1, 0x221)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 0x222)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G0, 0x223)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 0x224)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_HI12, 0x225)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_LO12, 0x226)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 0x227)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST8_TPREL_LO12, 0x228)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC, 0x229)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST16_TPREL_LO12, 0x22a)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC, 0x22b)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12, 0x22c)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC, 0x22d)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12, 0x22e)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC, 0x22f)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19, 0x230)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21, 0x231)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21, 0x232)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC, 0x233)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC, 0x234)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1, 0x235)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC, 0x236)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_LDR, 0x237)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_ADD, 0x238)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC_CALL, 0x239)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12, 0x23a)
|
||||
ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC, 0x23b)
|
||||
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12, 0x23c)
|
||||
ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC, 0x23d)
|
||||
|
||||
ELF_RELOC(R_AARCH64_COPY, 0x400)
|
||||
ELF_RELOC(R_AARCH64_GLOB_DAT, 0x401)
|
||||
ELF_RELOC(R_AARCH64_JUMP_SLOT, 0x402)
|
||||
ELF_RELOC(R_AARCH64_RELATIVE, 0x403)
|
||||
ELF_RELOC(R_AARCH64_TLS_DTPREL64, 0x404)
|
||||
ELF_RELOC(R_AARCH64_TLS_DTPMOD64, 0x405)
|
||||
ELF_RELOC(R_AARCH64_TLS_TPREL64, 0x406)
|
||||
ELF_RELOC(R_AARCH64_TLSDESC, 0x407)
|
||||
ELF_RELOC(R_AARCH64_IRELATIVE, 0x408)
|
||||
// ELF_RELOC(R_AARCH64_P32_NONE, 0)
|
||||
ELF_RELOC(R_AARCH64_P32_ABS32, 0x001)
|
||||
ELF_RELOC(R_AARCH64_P32_ABS16, 0x002)
|
||||
ELF_RELOC(R_AARCH64_P32_PREL32, 0x003)
|
||||
ELF_RELOC(R_AARCH64_P32_PREL16, 0x004)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_UABS_G0, 0x005)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_UABS_G0_NC, 0x006)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_UABS_G1, 0x007)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_SABS_G0, 0x008)
|
||||
ELF_RELOC(R_AARCH64_P32_LD_PREL_LO19, 0x009)
|
||||
ELF_RELOC(R_AARCH64_P32_ADR_PREL_LO21, 0x00a)
|
||||
ELF_RELOC(R_AARCH64_P32_ADR_PREL_PG_HI21, 0x00b)
|
||||
ELF_RELOC(R_AARCH64_P32_ADD_ABS_LO12_NC, 0x00c)
|
||||
ELF_RELOC(R_AARCH64_P32_LDST8_ABS_LO12_NC, 0x00d)
|
||||
ELF_RELOC(R_AARCH64_P32_TSTBR14, 0x012)
|
||||
ELF_RELOC(R_AARCH64_P32_CONDBR19, 0x013)
|
||||
ELF_RELOC(R_AARCH64_P32_JUMP26, 0x014)
|
||||
ELF_RELOC(R_AARCH64_P32_CALL26, 0x015)
|
||||
ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e)
|
||||
ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f)
|
||||
ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0, 0x016)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0_NC, 0x017)
|
||||
ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G1, 0x018)
|
||||
ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011)
|
||||
ELF_RELOC(R_AARCH64_P32_GOT_LD_PREL19, 0x019)
|
||||
ELF_RELOC(R_AARCH64_P32_ADR_GOT_PAGE, 0x01a)
|
||||
ELF_RELOC(R_AARCH64_P32_LD64_GOT_LO12_NC, 0x01b)
|
||||
ELF_RELOC(R_AARCH64_P32_LD32_GOTPAGE_LO14, 0x01c)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1, 0x057)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0, 0x058)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC, 0x059)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_DTPREL_HI12, 0x05a)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12, 0x05b)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC, 0x05c)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12, 0x05d)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC, 0x05e)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12, 0x05f)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC, 0x060)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12, 0x061)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC, 0x062)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12, 0x063)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC, 0x064)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21, 0x067)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, 0x068)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19, 0x069)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_MOVW_TPREL_G1, 0x06a)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_MOVW_TPREL_G0, 0x06b)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC, 0x06c)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_ADD_TPREL_HI12, 0x06d)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_ADD_TPREL_LO12, 0x06e)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC, 0x06f)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12, 0x070)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC, 0x071)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12, 0x072)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC, 0x073)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12, 0x074)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC, 0x075)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12, 0x076)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC, 0x077)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x051)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12_NC, 0x07d)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12_NC, 0x034)
|
||||
ELF_RELOC(R_AARCH64_P32_TLSDESC_CALL, 0x07f)
|
||||
ELF_RELOC(R_AARCH64_P32_COPY, 0x0b4)
|
||||
ELF_RELOC(R_AARCH64_P32_GLOB_DAT, 0x0b5)
|
||||
ELF_RELOC(R_AARCH64_P32_JUMP_SLOT, 0x0b6)
|
||||
ELF_RELOC(R_AARCH64_P32_RELATIVE, 0x0b7)
|
||||
ELF_RELOC(R_AARCH64_P32_IRELATIVE, 0x0bc)
|
||||
|
||||
@ -159,7 +159,11 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
|
||||
}
|
||||
|
||||
// Helper function to build a DataLayout string
|
||||
static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
|
||||
static std::string computeDataLayout(const Triple &TT,
|
||||
const MCTargetOptions &Options,
|
||||
bool LittleEndian) {
|
||||
if (Options.getABIName() == "ilp32")
|
||||
return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
|
||||
if (TT.isOSBinFormatMachO())
|
||||
return "e-m:o-i64:64-i128:128-n32:64-S128";
|
||||
if (LittleEndian)
|
||||
@ -188,8 +192,10 @@ AArch64TargetMachine::AArch64TargetMachine(
|
||||
CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
|
||||
// This nested ternary is horrible, but DL needs to be properly
|
||||
// initialized before TLInfo is constructed.
|
||||
: LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
|
||||
Options, getEffectiveRelocModel(TT, RM), CM, OL),
|
||||
: LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
|
||||
LittleEndian),
|
||||
TT, CPU, FS, Options,
|
||||
getEffectiveRelocModel(TT, RM), CM, OL),
|
||||
TLOF(createTLOF(getTargetTriple())),
|
||||
isLittle(LittleEndian) {
|
||||
initAsmInfo();
|
||||
|
||||
@ -119,9 +119,11 @@ public:
|
||||
#define GET_OPERAND_DIAGNOSTIC_TYPES
|
||||
#include "AArch64GenAsmMatcher.inc"
|
||||
};
|
||||
bool IsILP32;
|
||||
AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
|
||||
const MCInstrInfo &MII, const MCTargetOptions &Options)
|
||||
: MCTargetAsmParser(Options, STI) {
|
||||
IsILP32 = Options.getABIName() == "ilp32";
|
||||
MCAsmParserExtension::Initialize(Parser);
|
||||
MCStreamer &S = getParser().getStreamer();
|
||||
if (S.getTargetStreamer() == nullptr)
|
||||
@ -4690,7 +4692,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
|
||||
"consecutive same-size even/odd register pair");
|
||||
return MatchOperand_ParseFail;
|
||||
}
|
||||
|
||||
|
||||
unsigned Pair = 0;
|
||||
if(isXReg) {
|
||||
Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
|
||||
|
||||
@ -541,12 +541,14 @@ namespace {
|
||||
class ELFAArch64AsmBackend : public AArch64AsmBackend {
|
||||
public:
|
||||
uint8_t OSABI;
|
||||
bool IsILP32;
|
||||
|
||||
ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
|
||||
: AArch64AsmBackend(T, IsLittleEndian), OSABI(OSABI) {}
|
||||
ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian,
|
||||
bool IsILP32)
|
||||
: AArch64AsmBackend(T, IsLittleEndian), OSABI(OSABI), IsILP32(IsILP32) {}
|
||||
|
||||
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
|
||||
return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian);
|
||||
return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian, IsILP32);
|
||||
}
|
||||
|
||||
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
|
||||
@ -593,7 +595,8 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
|
||||
|
||||
assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
|
||||
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
||||
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
|
||||
bool IsILP32 = Options.getABIName() == "ilp32";
|
||||
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true, IsILP32);
|
||||
}
|
||||
|
||||
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
|
||||
@ -604,5 +607,6 @@ MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
|
||||
assert(TheTriple.isOSBinFormatELF() &&
|
||||
"Big endian is only supported for ELF targets!");
|
||||
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
||||
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false);
|
||||
bool IsILP32 = Options.getABIName() == "ilp32";
|
||||
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false, IsILP32);
|
||||
}
|
||||
|
||||
@ -25,25 +25,80 @@ using namespace llvm;
|
||||
namespace {
|
||||
class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
|
||||
public:
|
||||
AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
|
||||
AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian, bool IsILP32);
|
||||
|
||||
~AArch64ELFObjectWriter() override;
|
||||
|
||||
protected:
|
||||
unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
|
||||
const MCFixup &Fixup, bool IsPCRel) const override;
|
||||
|
||||
bool IsILP32;
|
||||
private:
|
||||
};
|
||||
}
|
||||
|
||||
AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
|
||||
bool IsLittleEndian)
|
||||
bool IsLittleEndian,
|
||||
bool IsILP32)
|
||||
: MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
|
||||
/*HasRelocationAddend*/ true) {}
|
||||
/*HasRelocationAddend*/ true),
|
||||
IsILP32(IsILP32) {}
|
||||
|
||||
AArch64ELFObjectWriter::~AArch64ELFObjectWriter() {}
|
||||
|
||||
#define R_CLS(rtype) \
|
||||
IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
|
||||
#define BAD_ILP32_MOV(lp64rtype) "ILP32 absolute MOV relocation not "\
|
||||
"supported (LP64 eqv: " #lp64rtype ")"
|
||||
|
||||
// assumes IsILP32 is true
|
||||
bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind,
|
||||
MCContext &Ctx)
|
||||
{
|
||||
if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
|
||||
return false;
|
||||
switch(RefKind) {
|
||||
case AArch64MCExpr::VK_ABS_G3:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
|
||||
return true;
|
||||
case AArch64MCExpr::VK_ABS_G2:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
|
||||
return true;
|
||||
case AArch64MCExpr::VK_ABS_G2_S:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_ABS_G2_NC:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_ABS_G1_S:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_ABS_G1_NC:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_DTPREL_G2:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_DTPREL_G1_NC:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_TPREL_G2:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_TPREL_G1_NC:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_GOTTPREL_G1:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64MCExpr::VK_GOTTPREL_G0_NC:
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
default: return false;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
|
||||
const MCValue &Target,
|
||||
const MCFixup &Fixup,
|
||||
@ -67,147 +122,161 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
|
||||
Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case FK_Data_2:
|
||||
return ELF::R_AARCH64_PREL16;
|
||||
return R_CLS(PREL16);
|
||||
case FK_Data_4:
|
||||
return ELF::R_AARCH64_PREL32;
|
||||
return R_CLS(PREL32);
|
||||
case FK_Data_8:
|
||||
return ELF::R_AARCH64_PREL64;
|
||||
if (IsILP32) {
|
||||
Ctx.reportError(Fixup.getLoc(), "ILP32 8 byte PC relative data "
|
||||
"relocation not supported (LP64 eqv: PREL64)");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
} else
|
||||
return ELF::R_AARCH64_PREL64;
|
||||
case AArch64::fixup_aarch64_pcrel_adr_imm21:
|
||||
assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation");
|
||||
return ELF::R_AARCH64_ADR_PREL_LO21;
|
||||
return R_CLS(ADR_PREL_LO21);
|
||||
case AArch64::fixup_aarch64_pcrel_adrp_imm21:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
|
||||
return ELF::R_AARCH64_ADR_PREL_PG_HI21;
|
||||
return R_CLS(ADR_PREL_PG_HI21);
|
||||
if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
|
||||
return ELF::R_AARCH64_ADR_GOT_PAGE;
|
||||
return R_CLS(ADR_GOT_PAGE);
|
||||
if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21;
|
||||
return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
|
||||
if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
|
||||
return ELF::R_AARCH64_TLSDESC_ADR_PAGE21;
|
||||
return R_CLS(TLSDESC_ADR_PAGE21);
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid symbol kind for ADRP relocation");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_pcrel_branch26:
|
||||
return ELF::R_AARCH64_JUMP26;
|
||||
return R_CLS(JUMP26);
|
||||
case AArch64::fixup_aarch64_pcrel_call26:
|
||||
return ELF::R_AARCH64_CALL26;
|
||||
return R_CLS(CALL26);
|
||||
case AArch64::fixup_aarch64_ldr_pcrel_imm19:
|
||||
if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
|
||||
return ELF::R_AARCH64_TLSIE_LD_GOTTPREL_PREL19;
|
||||
return ELF::R_AARCH64_LD_PREL_LO19;
|
||||
return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
|
||||
return R_CLS(LD_PREL_LO19);
|
||||
case AArch64::fixup_aarch64_pcrel_branch14:
|
||||
return ELF::R_AARCH64_TSTBR14;
|
||||
return R_CLS(TSTBR14);
|
||||
case AArch64::fixup_aarch64_pcrel_branch19:
|
||||
return ELF::R_AARCH64_CONDBR19;
|
||||
return R_CLS(CONDBR19);
|
||||
default:
|
||||
Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
}
|
||||
} else {
|
||||
if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
|
||||
return ELF::R_AARCH64_NONE;
|
||||
switch ((unsigned)Fixup.getKind()) {
|
||||
case FK_Data_1:
|
||||
Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case FK_Data_2:
|
||||
return ELF::R_AARCH64_ABS16;
|
||||
return R_CLS(ABS16);
|
||||
case FK_Data_4:
|
||||
return ELF::R_AARCH64_ABS32;
|
||||
return R_CLS(ABS32);
|
||||
case FK_Data_8:
|
||||
return ELF::R_AARCH64_ABS64;
|
||||
if (IsILP32) {
|
||||
Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(ABS64));
|
||||
return ELF::R_AARCH64_NONE;
|
||||
} else
|
||||
return ELF::R_AARCH64_ABS64;
|
||||
case AArch64::fixup_aarch64_add_imm12:
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
|
||||
return ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
|
||||
return R_CLS(TLSLD_ADD_DTPREL_HI12);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
|
||||
return ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
|
||||
return R_CLS(TLSLE_ADD_TPREL_HI12);
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
|
||||
return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
|
||||
return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
|
||||
return ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
|
||||
return R_CLS(TLSLD_ADD_DTPREL_LO12);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
|
||||
return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
|
||||
return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
|
||||
return ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
|
||||
return R_CLS(TLSLE_ADD_TPREL_LO12);
|
||||
if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
|
||||
return ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
|
||||
return R_CLS(TLSDESC_ADD_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_ADD_ABS_LO12_NC;
|
||||
return R_CLS(ADD_ABS_LO12_NC);
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for add (uimm12) instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_ldst_imm12_scale1:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_LDST8_ABS_LO12_NC;
|
||||
return R_CLS(LDST8_ABS_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12;
|
||||
return R_CLS(TLSLD_LDST8_DTPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC;
|
||||
return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12;
|
||||
return R_CLS(TLSLE_LDST8_TPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC;
|
||||
return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for 8-bit load/store instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_ldst_imm12_scale2:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_LDST16_ABS_LO12_NC;
|
||||
return R_CLS(LDST16_ABS_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12;
|
||||
return R_CLS(TLSLD_LDST16_DTPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC;
|
||||
return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12;
|
||||
return R_CLS(TLSLE_LDST16_TPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC;
|
||||
return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for 16-bit load/store instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_ldst_imm12_scale4:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_LDST32_ABS_LO12_NC;
|
||||
return R_CLS(LDST32_ABS_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12;
|
||||
return R_CLS(TLSLD_LDST32_DTPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC;
|
||||
return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12;
|
||||
return R_CLS(TLSLE_LDST32_TPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC;
|
||||
return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for 32-bit load/store instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_ldst_imm12_scale8:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_LDST64_ABS_LO12_NC;
|
||||
return R_CLS(LDST64_ABS_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_GOT && IsNC)
|
||||
return ELF::R_AARCH64_LD64_GOT_LO12_NC;
|
||||
return R_CLS(LD64_GOT_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12;
|
||||
return R_CLS(TLSLD_LDST64_DTPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC;
|
||||
return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12;
|
||||
return R_CLS(TLSLE_LDST64_TPREL_LO12);
|
||||
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC;
|
||||
return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
|
||||
if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC)
|
||||
return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
|
||||
return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC
|
||||
: ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
|
||||
if (SymLoc == AArch64MCExpr::VK_TLSDESC && IsNC)
|
||||
return ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
|
||||
return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC
|
||||
: ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for 64-bit load/store instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_ldst_imm12_scale16:
|
||||
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
|
||||
return ELF::R_AARCH64_LDST128_ABS_LO12_NC;
|
||||
return R_CLS(LDST128_ABS_LO12_NC);
|
||||
|
||||
Ctx.reportError(Fixup.getLoc(),
|
||||
"invalid fixup for 128-bit load/store instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
// ILP32 case not reached here, tested with isNonILP32reloc
|
||||
case AArch64::fixup_aarch64_movw:
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G3)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G3;
|
||||
@ -218,37 +287,37 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G2_NC;
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G1)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G1;
|
||||
return R_CLS(MOVW_UABS_G1);
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
|
||||
return ELF::R_AARCH64_MOVW_SABS_G1;
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G1_NC;
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G0)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G0;
|
||||
return R_CLS(MOVW_UABS_G0);
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
|
||||
return ELF::R_AARCH64_MOVW_SABS_G0;
|
||||
return R_CLS(MOVW_SABS_G0);
|
||||
if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
|
||||
return ELF::R_AARCH64_MOVW_UABS_G0_NC;
|
||||
return R_CLS(MOVW_UABS_G0_NC);
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
|
||||
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
|
||||
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1;
|
||||
return R_CLS(TLSLD_MOVW_DTPREL_G1);
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
|
||||
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
|
||||
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0;
|
||||
return R_CLS(TLSLD_MOVW_DTPREL_G0);
|
||||
if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
|
||||
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC;
|
||||
return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_G2)
|
||||
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_G1)
|
||||
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1;
|
||||
return R_CLS(TLSLE_MOVW_TPREL_G1);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
|
||||
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_G0)
|
||||
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0;
|
||||
return R_CLS(TLSLE_MOVW_TPREL_G0);
|
||||
if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
|
||||
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC;
|
||||
return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
|
||||
if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
|
||||
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
|
||||
if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
|
||||
@ -257,7 +326,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
|
||||
"invalid fixup for movz/movk instruction");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
case AArch64::fixup_aarch64_tlsdesc_call:
|
||||
return ELF::R_AARCH64_TLSDESC_CALL;
|
||||
return R_CLS(TLSDESC_CALL);
|
||||
default:
|
||||
Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
|
||||
return ELF::R_AARCH64_NONE;
|
||||
@ -269,8 +338,9 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
|
||||
|
||||
MCObjectWriter *llvm::createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
|
||||
uint8_t OSABI,
|
||||
bool IsLittleEndian) {
|
||||
bool IsLittleEndian,
|
||||
bool IsILP32) {
|
||||
MCELFObjectTargetWriter *MOTW =
|
||||
new AArch64ELFObjectWriter(OSABI, IsLittleEndian);
|
||||
new AArch64ELFObjectWriter(OSABI, IsLittleEndian, IsILP32);
|
||||
return createELFObjectWriter(MOTW, OS, IsLittleEndian);
|
||||
}
|
||||
|
||||
@ -53,7 +53,8 @@ MCAsmBackend *createAArch64beAsmBackend(const Target &T,
|
||||
|
||||
MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
|
||||
uint8_t OSABI,
|
||||
bool IsLittleEndian);
|
||||
bool IsLittleEndian,
|
||||
bool IsILP32);
|
||||
|
||||
MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,
|
||||
uint32_t CPUType,
|
||||
|
||||
245
test/MC/AArch64/arm32-elf-relocs.s
Normal file
245
test/MC/AArch64/arm32-elf-relocs.s
Normal file
@ -0,0 +1,245 @@
|
||||
// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
|
||||
// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \
|
||||
// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
|
||||
// RUN: FileCheck %s --check-prefix=CHECK-OBJ-ILP32
|
||||
|
||||
add x0, x2, #:lo12:sym
|
||||
// CHECK: add x0, x2, :lo12:sym
|
||||
// CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
|
||||
|
||||
add x5, x7, #:dtprel_lo12:sym
|
||||
// CHECK: add x5, x7, :dtprel_lo12:sym
|
||||
// CHECK-OBJ-ILP32: 4 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym
|
||||
|
||||
add x9, x12, #:dtprel_lo12_nc:sym
|
||||
// CHECK: add x9, x12, :dtprel_lo12_nc:sym
|
||||
// CHECK-OBJ-ILP32: 8 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym
|
||||
|
||||
add x20, x30, #:tprel_lo12:sym
|
||||
// CHECK: add x20, x30, :tprel_lo12:sym
|
||||
// CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
|
||||
|
||||
add x9, x12, #:tprel_lo12_nc:sym
|
||||
// CHECK: add x9, x12, :tprel_lo12_nc:sym
|
||||
// CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
|
||||
|
||||
add x5, x0, #:tlsdesc_lo12:sym
|
||||
// CHECK: add x5, x0, :tlsdesc_lo12:sym
|
||||
// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym
|
||||
|
||||
add x0, x2, #:lo12:sym+8
|
||||
// CHECK: add x0, x2, :lo12:sym
|
||||
// CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+8
|
||||
|
||||
add x5, x7, #:dtprel_lo12:sym+1
|
||||
// CHECK: add x5, x7, :dtprel_lo12:sym+1
|
||||
// CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+1
|
||||
|
||||
add x9, x12, #:dtprel_lo12_nc:sym+2
|
||||
// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
|
||||
// CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+2
|
||||
|
||||
add x20, x30, #:tprel_lo12:sym+12
|
||||
// CHECK: add x20, x30, :tprel_lo12:sym+12
|
||||
// CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+12
|
||||
|
||||
add x9, x12, #:tprel_lo12_nc:sym+54
|
||||
// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
|
||||
// CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+54
|
||||
|
||||
add x5, x0, #:tlsdesc_lo12:sym+70
|
||||
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
|
||||
// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70
|
||||
|
||||
.hword sym + 4 - .
|
||||
// CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
|
||||
.word sym - . + 8
|
||||
// CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8
|
||||
|
||||
.hword sym
|
||||
// CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym
|
||||
.word sym+1
|
||||
// CHECK-OBJ-ILP32 40 R_AARCH64_P32_ABS32 sym+1
|
||||
|
||||
adrp x0, sym
|
||||
// CHECK: adrp x0, sym
|
||||
// CHECK-OBJ-ILP32 4c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
|
||||
|
||||
adrp x15, :got:sym
|
||||
// CHECK: adrp x15, :got:sym
|
||||
// CHECK-OBJ-ILP32 50 R_AARCH64_P32_ADR_GOT_PAGE sym
|
||||
|
||||
adrp x29, :gottprel:sym
|
||||
// CHECK: adrp x29, :gottprel:sym
|
||||
// CHECK-OBJ-ILP32 54 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
|
||||
|
||||
adrp x2, :tlsdesc:sym
|
||||
// CHECK: adrp x2, :tlsdesc:sym
|
||||
// CHECK-OBJ-ILP32 58 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
|
||||
|
||||
// LLVM is not competent enough to do this relocation because the
|
||||
// page boundary could occur anywhere after linking. A relocation
|
||||
// is needed.
|
||||
adrp x3, trickQuestion
|
||||
.global trickQuestion
|
||||
trickQuestion:
|
||||
// CHECK: adrp x3, trickQuestion
|
||||
// CHECK-OBJ-ILP32 5c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
|
||||
|
||||
ldrb w2, [x3, :lo12:sym]
|
||||
ldrsb w5, [x7, #:lo12:sym]
|
||||
ldrsb x11, [x13, :lo12:sym]
|
||||
ldr b17, [x19, #:lo12:sym]
|
||||
// CHECK: ldrb w2, [x3, :lo12:sym]
|
||||
// CHECK: ldrsb w5, [x7, :lo12:sym]
|
||||
// CHECK: ldrsb x11, [x13, :lo12:sym]
|
||||
// CHECK: ldr b17, [x19, :lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
|
||||
|
||||
ldrb w23, [x29, #:dtprel_lo12_nc:sym]
|
||||
ldrsb w23, [x19, #:dtprel_lo12:sym]
|
||||
ldrsb x17, [x13, :dtprel_lo12_nc:sym]
|
||||
ldr b11, [x7, #:dtprel_lo12:sym]
|
||||
// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
|
||||
ldrb w1, [x2, :tprel_lo12:sym]
|
||||
ldrsb w3, [x4, #:tprel_lo12_nc:sym]
|
||||
ldrsb x5, [x6, :tprel_lo12:sym]
|
||||
ldr b7, [x8, #:tprel_lo12_nc:sym]
|
||||
// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
|
||||
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
|
||||
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
|
||||
ldrh w2, [x3, #:lo12:sym]
|
||||
ldrsh w5, [x7, :lo12:sym]
|
||||
ldrsh x11, [x13, #:lo12:sym]
|
||||
ldr h17, [x19, :lo12:sym]
|
||||
// CHECK: ldrh w2, [x3, :lo12:sym]
|
||||
// CHECK: ldrsh w5, [x7, :lo12:sym]
|
||||
// CHECK: ldrsh x11, [x13, :lo12:sym]
|
||||
// CHECK: ldr h17, [x19, :lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
|
||||
|
||||
ldrh w23, [x29, #:dtprel_lo12_nc:sym]
|
||||
ldrsh w23, [x19, :dtprel_lo12:sym]
|
||||
ldrsh x17, [x13, :dtprel_lo12_nc:sym]
|
||||
ldr h11, [x7, #:dtprel_lo12:sym]
|
||||
// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
|
||||
ldrh w1, [x2, :tprel_lo12:sym]
|
||||
ldrsh w3, [x4, #:tprel_lo12_nc:sym]
|
||||
ldrsh x5, [x6, :tprel_lo12:sym]
|
||||
ldr h7, [x8, #:tprel_lo12_nc:sym]
|
||||
// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
|
||||
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
|
||||
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
|
||||
ldr w1, [x2, #:lo12:sym]
|
||||
ldrsw x3, [x4, #:lo12:sym]
|
||||
ldr s4, [x5, :lo12:sym]
|
||||
// CHECK: ldr w1, [x2, :lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :lo12:sym]
|
||||
// CHECK: ldr s4, [x5, :lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
|
||||
|
||||
ldr w1, [x2, :dtprel_lo12:sym]
|
||||
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
|
||||
ldr s4, [x5, #:dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
|
||||
|
||||
ldr w1, [x2, #:tprel_lo12:sym]
|
||||
ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
||||
ldr s4, [x5, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldr w1, [x2, :tprel_lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
|
||||
ldr x28, [x27, :lo12:sym]
|
||||
ldr d26, [x25, #:lo12:sym]
|
||||
// CHECK: ldr x28, [x27, :lo12:sym]
|
||||
// CHECK: ldr d26, [x25, :lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, #:got_lo12:sym]
|
||||
ldr d22, [x21, :got_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :got_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :got_lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, :dtprel_lo12_nc:sym]
|
||||
ldr d22, [x21, #:dtprel_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
|
||||
|
||||
ldr x24, [x23, #:tprel_lo12:sym]
|
||||
ldr d22, [x21, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldr x24, [x23, :tprel_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
|
||||
|
||||
# ldr x24, [x23, :gottprel_lo12:sym]
|
||||
# ldr d22, [x21, #:gottprel_lo12:sym]
|
||||
|
||||
ldr x24, [x23, #:tlsdesc_lo12:sym]
|
||||
ldr d22, [x21, :tlsdesc_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
|
||||
// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture
|
||||
// (AArch64) beta" doesn't have that.
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym
|
||||
|
||||
ldr q20, [x19, #:lo12:sym]
|
||||
// CHECK: ldr q20, [x19, :lo12:sym]
|
||||
// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym
|
||||
|
||||
// Since relocated instructions print without a '#', that syntax should
|
||||
// certainly be accepted when assembling.
|
||||
add x3, x5, :lo12:imm
|
||||
// CHECK: add x3, x5, :lo12:imm
|
||||
@ -1,83 +1,85 @@
|
||||
// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
|
||||
// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
|
||||
// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \
|
||||
// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
|
||||
// RUN: FileCheck %s --check-prefix=CHECK-OBJ-LP64
|
||||
|
||||
add x0, x2, #:lo12:sym
|
||||
// CHECK: add x0, x2, :lo12:sym
|
||||
// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64: 0 R_AARCH64_ADD_ABS_LO12_NC sym
|
||||
|
||||
add x5, x7, #:dtprel_lo12:sym
|
||||
// CHECK: add x5, x7, :dtprel_lo12:sym
|
||||
// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
|
||||
|
||||
add x9, x12, #:dtprel_lo12_nc:sym
|
||||
// CHECK: add x9, x12, :dtprel_lo12_nc:sym
|
||||
// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
|
||||
|
||||
add x20, x30, #:tprel_lo12:sym
|
||||
// CHECK: add x20, x30, :tprel_lo12:sym
|
||||
// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
|
||||
|
||||
add x9, x12, #:tprel_lo12_nc:sym
|
||||
// CHECK: add x9, x12, :tprel_lo12_nc:sym
|
||||
// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
|
||||
|
||||
add x5, x0, #:tlsdesc_lo12:sym
|
||||
// CHECK: add x5, x0, :tlsdesc_lo12:sym
|
||||
// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
|
||||
// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
|
||||
|
||||
add x0, x2, #:lo12:sym+8
|
||||
// CHECK: add x0, x2, :lo12:sym
|
||||
// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
|
||||
// CHECK-OBJ-LP64: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
|
||||
|
||||
add x5, x7, #:dtprel_lo12:sym+1
|
||||
// CHECK: add x5, x7, :dtprel_lo12:sym+1
|
||||
// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
|
||||
// CHECK-OBJ-LP64: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
|
||||
|
||||
add x9, x12, #:dtprel_lo12_nc:sym+2
|
||||
// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
|
||||
// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
|
||||
// CHECK-OBJ-LP64:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
|
||||
|
||||
add x20, x30, #:tprel_lo12:sym+12
|
||||
// CHECK: add x20, x30, :tprel_lo12:sym+12
|
||||
// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
|
||||
// CHECK-OBJ-LP64: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
|
||||
|
||||
add x9, x12, #:tprel_lo12_nc:sym+54
|
||||
// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
|
||||
// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
|
||||
// CHECK-OBJ-LP64: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
|
||||
|
||||
add x5, x0, #:tlsdesc_lo12:sym+70
|
||||
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
|
||||
// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
|
||||
// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
|
||||
|
||||
.hword sym + 4 - .
|
||||
// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
|
||||
// CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4
|
||||
.word sym - . + 8
|
||||
// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
|
||||
// CHECK-OBJ-LP64 32 R_AARCH64_PREL32 sym+8
|
||||
.xword sym-.
|
||||
// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
|
||||
// CHECK-OBJ-LP64 36 R_AARCH64_PREL64 sym{{$}}
|
||||
|
||||
.hword sym
|
||||
// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
|
||||
// CHECK-OBJ-LP64 3e R_AARCH64_ABS16 sym
|
||||
.word sym+1
|
||||
// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
|
||||
// CHECK-OBJ-LP64 40 R_AARCH64_ABS32 sym+1
|
||||
.xword sym+16
|
||||
// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
|
||||
// CHECK-OBJ-LP64 44 R_AARCH64_ABS64 sym+16
|
||||
|
||||
adrp x0, sym
|
||||
// CHECK: adrp x0, sym
|
||||
// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
|
||||
// CHECK-OBJ-LP64 4c R_AARCH64_ADR_PREL_PG_HI21 sym
|
||||
|
||||
adrp x15, :got:sym
|
||||
// CHECK: adrp x15, :got:sym
|
||||
// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
|
||||
// CHECK-OBJ-LP64 50 R_AARCH64_ADR_GOT_PAGE sym
|
||||
|
||||
adrp x29, :gottprel:sym
|
||||
// CHECK: adrp x29, :gottprel:sym
|
||||
// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
|
||||
// CHECK-OBJ-LP64 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
|
||||
|
||||
adrp x2, :tlsdesc:sym
|
||||
// CHECK: adrp x2, :tlsdesc:sym
|
||||
// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
|
||||
// CHECK-OBJ-LP64 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
|
||||
|
||||
// LLVM is not competent enough to do this relocation because the
|
||||
// page boundary could occur anywhere after linking. A relocation
|
||||
@ -86,7 +88,7 @@
|
||||
.global trickQuestion
|
||||
trickQuestion:
|
||||
// CHECK: adrp x3, trickQuestion
|
||||
// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
|
||||
// CHECK-OBJ-LP64 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
|
||||
|
||||
ldrb w2, [x3, :lo12:sym]
|
||||
ldrsb w5, [x7, #:lo12:sym]
|
||||
@ -96,10 +98,10 @@ trickQuestion:
|
||||
// CHECK: ldrsb w5, [x7, :lo12:sym]
|
||||
// CHECK: ldrsb x11, [x13, :lo12:sym]
|
||||
// CHECK: ldr b17, [x19, :lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
|
||||
|
||||
ldrb w23, [x29, #:dtprel_lo12_nc:sym]
|
||||
ldrsb w23, [x19, #:dtprel_lo12:sym]
|
||||
@ -109,10 +111,10 @@ trickQuestion:
|
||||
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
|
||||
|
||||
ldrb w1, [x2, :tprel_lo12:sym]
|
||||
ldrsb w3, [x4, #:tprel_lo12_nc:sym]
|
||||
@ -122,10 +124,10 @@ trickQuestion:
|
||||
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
|
||||
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
|
||||
|
||||
ldrh w2, [x3, #:lo12:sym]
|
||||
ldrsh w5, [x7, :lo12:sym]
|
||||
@ -135,10 +137,10 @@ trickQuestion:
|
||||
// CHECK: ldrsh w5, [x7, :lo12:sym]
|
||||
// CHECK: ldrsh x11, [x13, :lo12:sym]
|
||||
// CHECK: ldr h17, [x19, :lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
|
||||
|
||||
ldrh w23, [x29, #:dtprel_lo12_nc:sym]
|
||||
ldrsh w23, [x19, :dtprel_lo12:sym]
|
||||
@ -148,10 +150,10 @@ trickQuestion:
|
||||
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
|
||||
|
||||
ldrh w1, [x2, :tprel_lo12:sym]
|
||||
ldrsh w3, [x4, #:tprel_lo12_nc:sym]
|
||||
@ -161,10 +163,10 @@ trickQuestion:
|
||||
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
|
||||
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
|
||||
|
||||
ldr w1, [x2, #:lo12:sym]
|
||||
ldrsw x3, [x4, #:lo12:sym]
|
||||
@ -172,9 +174,9 @@ trickQuestion:
|
||||
// CHECK: ldr w1, [x2, :lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :lo12:sym]
|
||||
// CHECK: ldr s4, [x5, :lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
|
||||
|
||||
ldr w1, [x2, :dtprel_lo12:sym]
|
||||
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
|
||||
@ -182,9 +184,9 @@ trickQuestion:
|
||||
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
|
||||
|
||||
|
||||
ldr w1, [x2, #:tprel_lo12:sym]
|
||||
@ -193,55 +195,55 @@ trickQuestion:
|
||||
// CHECK: ldr w1, [x2, :tprel_lo12:sym]
|
||||
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
|
||||
|
||||
ldr x28, [x27, :lo12:sym]
|
||||
ldr d26, [x25, #:lo12:sym]
|
||||
// CHECK: ldr x28, [x27, :lo12:sym]
|
||||
// CHECK: ldr d26, [x25, :lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST64_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST64_ABS_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, #:got_lo12:sym]
|
||||
ldr d22, [x21, :got_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :got_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :got_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LD64_GOT_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LD64_GOT_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, :dtprel_lo12_nc:sym]
|
||||
ldr d22, [x21, #:dtprel_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
|
||||
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
|
||||
|
||||
ldr x24, [x23, #:tprel_lo12:sym]
|
||||
ldr d22, [x21, :tprel_lo12_nc:sym]
|
||||
// CHECK: ldr x24, [x23, :tprel_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, :gottprel_lo12:sym]
|
||||
ldr d22, [x21, #:gottprel_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
|
||||
|
||||
ldr x24, [x23, #:tlsdesc_lo12:sym]
|
||||
ldr d22, [x21, :tlsdesc_lo12:sym]
|
||||
// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
|
||||
// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
|
||||
// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
|
||||
|
||||
ldr q20, [x19, #:lo12:sym]
|
||||
// CHECK: ldr q20, [x19, :lo12:sym]
|
||||
// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
|
||||
// CHECK-OBJ-LP64 R_AARCH64_LDST128_ABS_LO12_NC sym
|
||||
|
||||
// Since relocated instructions print without a '#', that syntax should
|
||||
// certainly be accepted when assembling.
|
||||
|
||||
37
test/MC/AArch64/arm64-ilp32.s
Normal file
37
test/MC/AArch64/arm64-ilp32.s
Normal file
@ -0,0 +1,37 @@
|
||||
// RUN: llvm-mc -target-abi=ilp32 -triple aarch64-non-linux-gnu -filetype=obj \
|
||||
// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-ILP32 %s
|
||||
// RUN: llvm-mc -triple aarch64-non-linux-gnu -filetype=obj \
|
||||
// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-LP64 %s
|
||||
.text
|
||||
.file "../projects/clang/test/Driver/arm64-ilp32.c"
|
||||
.globl foo
|
||||
.align 2
|
||||
.type foo,@function
|
||||
foo: // @foo
|
||||
// BB#0: // %entry
|
||||
sub sp, sp, #16 // =16
|
||||
// CHECK-ILP32: 0000000000000004 R_AARCH64_P32_ADR_PREL_PG_HI21 sizes
|
||||
// CHECK-ILP32: 0000000000000008 R_AARCH64_P32_ADD_ABS_LO12_NC sizes
|
||||
// CHECK-LP64: 0000000000000004 R_AARCH64_ADR_PREL_PG_HI21 sizes
|
||||
// CHECK-LP64: 0000000000000008 R_AARCH64_ADD_ABS_LO12_NC sizes
|
||||
adrp x8, sizes
|
||||
add x8, x8, :lo12:sizes
|
||||
str w0, [sp, #12]
|
||||
str w1, [sp, #8]
|
||||
ldr w0, [x8]
|
||||
add sp, sp, #16 // =16
|
||||
ret
|
||||
.Lfunc_end0:
|
||||
.size foo, .Lfunc_end0-foo
|
||||
|
||||
.type sizes,@object // @sizes
|
||||
.data
|
||||
.globl sizes
|
||||
.align 2
|
||||
sizes:
|
||||
.word 1 // 0x1
|
||||
.word 2 // 0x2
|
||||
.word 4 // 0x4
|
||||
.word 4 // 0x4
|
||||
.word 4 // 0x4
|
||||
.size sizes, 20
|
||||
67
test/MC/AArch64/ilp32-diagnostics.s
Normal file
67
test/MC/AArch64/ilp32-diagnostics.s
Normal file
@ -0,0 +1,67 @@
|
||||
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -target-abi=ilp32 \
|
||||
// RUN: < %s 2> %t2 -filetype=obj
|
||||
// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t2
|
||||
|
||||
.xword sym-.
|
||||
// CHECK-ERROR: error: ILP32 8 byte PC relative data relocation not supported (LP64 eqv: PREL64)
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x7, #:abs_g3:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G3)
|
||||
// CHECK-ERROR: movz x7, #:abs_g3:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x3, #:abs_g2:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G2)
|
||||
// CHECK-ERROR: movz x3, #:abs_g2:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x19, #:abs_g2_s:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_SABS_G2)
|
||||
// CHECK-ERROR: movz x19, #:abs_g2_s:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movk x5, #:abs_g2_nc:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G2_NC)
|
||||
// CHECK-ERROR: movk x5, #:abs_g2_nc:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x19, #:abs_g1_s:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_SABS_G1)
|
||||
// CHECK-ERROR: movz x19, #:abs_g1_s:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movk x5, #:abs_g1_nc:some_label
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G1_NC)
|
||||
// CHECK-ERROR: movk x5, #:abs_g1_nc:some_label
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x3, #:dtprel_g2:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLD_MOVW_DTPREL_G2)
|
||||
// CHECK-ERROR: movz x3, #:dtprel_g2:var
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movk x9, #:dtprel_g1_nc:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLD_MOVW_DTPREL_G1_NC)
|
||||
// CHECK-ERROR: movk x9, #:dtprel_g1_nc:var
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x3, #:tprel_g2:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLE_MOVW_TPREL_G2)
|
||||
// CHECK-ERROR: movz x3, #:tprel_g2:var
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movk x9, #:tprel_g1_nc:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLE_MOVW_TPREL_G1_NC)
|
||||
// CHECK-ERROR: movk x9, #:tprel_g1_nc:var
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movz x15, #:gottprel_g1:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSIE_MOVW_GOTTPREL_G1)
|
||||
// CHECK-ERROR: movz x15, #:gottprel_g1:var
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
movk x13, #:gottprel_g0_nc:var
|
||||
// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSIE_MOVW_GOTTPREL_G0_NC)
|
||||
// CHECK-ERROR: movk x13, #:gottprel_g0_nc:var
|
||||
// CHECK-ERROR: ^
|
||||
@ -715,6 +715,94 @@ class Relocs_Elf_AArch64(Enum):
|
||||
R_AARCH64_TLSDESC = 0x407
|
||||
R_AARCH64_IRELATIVE = 0x408
|
||||
|
||||
class Relocs_Elf_AArch64_ILP32(Enum):
|
||||
R_AARCH64_P32_NONE = 0
|
||||
R_AARCH64_P32_ABS32 = 1
|
||||
R_AARCH64_P32_ABS16 = 2
|
||||
R_AARCH64_P32_PREL32 = 3
|
||||
R_AARCH64_P32_PREL16 = 4
|
||||
R_AARCH64_P32_MOVW_UABS_G0 = 5
|
||||
R_AARCH64_P32_MOVW_UABS_G0_NC = 6
|
||||
R_AARCH64_P32_MOVW_UABS_G1 = 7
|
||||
R_AARCH64_P32_MOVW_SABS_G0 = 8
|
||||
R_AARCH64_P32_LD_PREL_LO19 = 9
|
||||
R_AARCH64_P32_ADR_PREL_LO21 = 10
|
||||
R_AARCH64_P32_ADR_PREL_PG_HI21 = 11
|
||||
R_AARCH64_P32_ADD_ABS_LO12_NC = 12
|
||||
R_AARCH64_P32_LDST8_ABS_LO12_NC = 13
|
||||
R_AARCH64_P32_LDST16_ABS_LO12_NC = 14
|
||||
R_AARCH64_P32_LDST32_ABS_LO12_NC = 15
|
||||
R_AARCH64_P32_LDST64_ABS_LO12_NC = 16
|
||||
R_AARCH64_P32_LDST128_ABS_LO12_NC = 17
|
||||
R_AARCH64_P32_TSTBR14 = 18
|
||||
R_AARCH64_P32_CONDBR19 = 19
|
||||
R_AARCH64_P32_JUMP26 = 20
|
||||
R_AARCH64_P32_CALL26 = 21
|
||||
R_AARCH64_P32_MOVW_PREL_G0 = 22
|
||||
R_AARCH64_P32_MOVW_PREL_G0_NC = 23
|
||||
R_AARCH64_P32_MOVW_PREL_G1 = 24
|
||||
R_AARCH64_P32_GOT_LD_PREL19 = 25
|
||||
R_AARCH64_P32_ADR_GOT_PAGE = 26
|
||||
R_AARCH64_P32_LD32_GOT_LO12_NC = 27
|
||||
R_AARCH64_P32_LD32_GOTPAGE_LO14 = 28
|
||||
R_AARCH64_P32_TLSGD_ADR_PREL21 = 80
|
||||
R_AARCH64_P32_TLS_GD_ADR_PAGE21 = 81
|
||||
R_AARCH64_P32_TLSGD_ADD_LO12_NC = 82
|
||||
R_AARCH64_P32_TLSLD_ADR_PREL21 = 83
|
||||
R_AARCH64_P32_TLDLD_ADR_PAGE21 = 84
|
||||
R_AARCH64_P32_TLSLD_ADR_LO12_NC = 85
|
||||
R_AARCH64_P32_TLSLD_LD_PREL19 = 86
|
||||
R_AARCH64_P32_TLDLD_MOVW_DTPREL_G1 = 87
|
||||
R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 = 88
|
||||
R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC = 89
|
||||
R_AARCH64_P32_TLSLD_MOVW_ADD_DTPREL_HI12 = 90
|
||||
R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 = 91
|
||||
R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC = 92
|
||||
R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 = 93
|
||||
R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC = 94
|
||||
R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 = 95
|
||||
R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC = 96
|
||||
R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 = 97
|
||||
R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC = 98
|
||||
R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 = 99
|
||||
R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC = 100
|
||||
R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 = 101
|
||||
R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC = 102
|
||||
R_AARCH64_P32_TLSIE_MOVW_GOTTPREL_PAGE21 = 103
|
||||
R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC = 104
|
||||
R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19 = 105
|
||||
R_AARCH64_P32_TLSLE_MOVEW_TPREL_G1 = 106
|
||||
R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 = 107
|
||||
R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC = 108
|
||||
R_AARCH64_P32_TLS_MOVW_TPREL_HI12 = 109
|
||||
R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 = 110
|
||||
R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC = 111
|
||||
R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 = 112
|
||||
R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC = 113
|
||||
R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 = 114
|
||||
R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC = 115
|
||||
R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 = 116
|
||||
R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC = 117
|
||||
R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 = 118
|
||||
R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC = 119
|
||||
R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 = 120
|
||||
R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC = 121
|
||||
R_AARCH64_P32_TLSDESC_LD_PRELL19 = 122
|
||||
R_AARCH64_P32_TLSDESC_ADR_PREL21 = 123
|
||||
R_AARCH64_P32_TLSDESC_ADR_PAGE21 = 124
|
||||
R_AARCH64_P32_TLSDESSC_LD32_LO12 = 125
|
||||
R_AARCH64_P32_TLSDESC_ADD_LO12 = 126
|
||||
R_AARCH64_P32_TLSDESC_CALL = 127
|
||||
R_AARCH64_P32_COPY = 180
|
||||
R_AARCH64_P32_GLOB_DAT = 181
|
||||
R_AARCH64_P32_JUMP_SLOT = 182
|
||||
R_AARCH64_P32_RELATIVE = 183
|
||||
R_AARCH64_P32_TLS_DTPREL = 184
|
||||
R_AARCH64_P32_TLS_DTPMOD = 185
|
||||
R_AARCH64_P32_TLS_TPREL = 186
|
||||
R_AARCH64_P32_TLSDESC = 187
|
||||
R_AARCH64_P32_IRELATIVE = 188
|
||||
|
||||
class Relocs_Elf_ARM(Enum):
|
||||
R_ARM_NONE = 0x00
|
||||
R_ARM_PC24 = 0x01
|
||||
@ -1107,6 +1195,9 @@ craftElf("relocs.obj.elf-i386", "i386-pc-linux-gnu", Relocs_Elf_i3
|
||||
craftElf("relocs.obj.elf-ppc64", "powerpc64-unknown-linux-gnu", Relocs_Elf_PPC64.entries(),
|
||||
("@t = thread_local global i32 0, align 4", "define i32* @f{0}() nounwind {{ ret i32* @t }}", 2))
|
||||
craftElf("relocs.obj.elf-aarch64", "aarch64", Relocs_Elf_AArch64.entries(), "movz x0, #:abs_g0:sym")
|
||||
craftElf("relocs.obj.elf-aarch64-ilp32", "aarch64",
|
||||
Relocs_Elf_AArch64_ILP32.entries(), "movz x0, #:abs_g0:sym")
|
||||
Relocs_Elf_AArch64_ILP32
|
||||
craftElf("relocs.obj.elf-arm", "arm-unknown-unknown", Relocs_Elf_ARM.entries(), "b sym")
|
||||
craftElf("relocs.obj.elf-mips", "mips-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
|
||||
craftElf("relocs.obj.elf-mips64el", "mips64el-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user