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Pseudo-ize VMOVDcc and VMOVScc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-03-11 23:09:50 +00:00
parent b181ad3486
commit f219f3135d
3 changed files with 19 additions and 9 deletions
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13
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -708,6 +708,19 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
switch (Opcode) {
default:
return false;
case ARM::VMOVScc:
case ARM::VMOVDcc: {
unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg());
MI.eraseFromParent();
return true;
}
case ARM::MOVCCr: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr),
MI.getOperand(1).getReg())

10
lib/Target/ARM/ARMInstrVFP.td
View File

@ -972,15 +972,13 @@ def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
//
let neverHasSideEffects = 1 in {
def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
Size4Bytes, IIC_fpUNA64,
[/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
RegConstraint<"$Dn = $Dd">;
def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
Size4Bytes, IIC_fpUNA32,
[/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
RegConstraint<"$Sn = $Sd">;
} // neverHasSideEffects

5
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1600,9 +1600,8 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "FNEGDcc")
return false;
// Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc.
if (Name == "VMOVDcc" || Name == "VMOVScc" || Name == "VNEGDcc" ||
Name == "VNEGScc")
// Ditto for VNEGDcc and VNEGScc.
if (Name == "VNEGDcc" || Name == "VNEGScc")
return false;
// LDMIA_RET is a special case of LDM (Load Multiple) where the registers