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XCore target: Add byval handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lytton
parent
98369fb0e7
commit
f2617291e3
@ -1031,6 +1031,10 @@ XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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// Formal Arguments Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
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}
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/// XCore formal arguments implementation
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SDValue
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XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
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@ -1080,11 +1084,22 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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unsigned LRSaveSize = StackSlotSize;
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// TODO: need to make copies of any byVal arguments
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// All getCopyFromReg ops must precede any getMemcpys to prevent the
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// scheduler clobbering a register before it has been copied.
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// The stages are:
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// 1. CopyFromReg (and load) arg & vararg registers.
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// 2. Chain CopyFromReg nodes into a TokenFactor.
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// 3. Memcpy 'byVal' args & push final InVals.
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// 4. Chain mem ops nodes into a TokenFactor.
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SmallVector<SDValue, 4> CFRegNode;
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SmallVector<ArgDataPair, 4> ArgData;
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SmallVector<SDValue, 4> MemOps;
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// 1a. CopyFromReg (and load) arg registers.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue ArgIn;
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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@ -1101,7 +1116,8 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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case MVT::i32:
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unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
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ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
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CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
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}
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} else {
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// sanity check
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@ -1121,14 +1137,17 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
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InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
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ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
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MachinePointerInfo::getFixedStack(FI),
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false, false, false, 0));
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false, false, false, 0);
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}
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const ArgDataPair ADP = { ArgIn, Ins[i].Flags };
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ArgData.push_back(ADP);
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}
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// 1b. CopyFromReg vararg registers.
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if (isVarArg) {
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/* Argument registers */
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// Argument registers
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static const uint16_t ArgRegs[] = {
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XCore::R0, XCore::R1, XCore::R2, XCore::R3
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};
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@ -1136,7 +1155,6 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
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array_lengthof(ArgRegs));
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if (FirstVAReg < array_lengthof(ArgRegs)) {
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SmallVector<SDValue, 4> MemOps;
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int offset = 0;
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// Save remaining registers, storing higher register numbers at a higher
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// address
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@ -1152,14 +1170,12 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
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RegInfo.addLiveIn(ArgRegs[i], VReg);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
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// Move argument from virt reg -> stack
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(), false, false, 0);
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MemOps.push_back(Store);
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}
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if (!MemOps.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOps[0], MemOps.size());
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} else {
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// This will point to the next argument passed via stack.
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XFI->setVarArgsFrameIndex(
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@ -1168,6 +1184,42 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
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}
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}
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// 2. chain CopyFromReg nodes into a TokenFactor.
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if (!CFRegNode.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &CFRegNode[0],
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CFRegNode.size());
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// 3. Memcpy 'byVal' args & push final InVals.
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// Aggregates passed "byVal" need to be copied by the callee.
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// The callee will use a pointer to this copy, rather than the original
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// pointer.
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for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(),
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ArgDE = ArgData.end();
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ArgDI != ArgDE; ++ArgDI) {
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if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) {
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unsigned Size = ArgDI->Flags.getByValSize();
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unsigned Align = ArgDI->Flags.getByValAlign();
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// Create a new object on the stack and copy the pointee into it.
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int FI = MFI->CreateStackObject(Size, Align, false, false);
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
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InVals.push_back(FIN);
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MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
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DAG.getConstant(Size, MVT::i32),
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Align, false, false,
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MachinePointerInfo(),
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MachinePointerInfo()));
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} else {
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InVals.push_back(ArgDI->SDV);
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}
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}
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// 4, chain mem ops nodes into a TokenFactor.
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if (!MemOps.empty()) {
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MemOps.push_back(Chain);
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
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MemOps.size());
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}
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return Chain;
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}
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58
test/CodeGen/XCore/byVal.ll
Normal file
58
test/CodeGen/XCore/byVal.ll
Normal file
@ -0,0 +1,58 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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; CHECK-LABEL: f0Test
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; CHECK: entsp 1
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; CHECK: bl f0
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; CHECK: retsp 1
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%struct.st0 = type { [0 x i32] }
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declare void @f0(%struct.st0*) nounwind
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define void @f0Test(%struct.st0* byval %s0) nounwind {
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entry:
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call void @f0(%struct.st0* %s0) nounwind
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ret void
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}
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; CHECK-LABEL: f1Test
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; CHECK: entsp 13
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; CHECK: stw r4, sp[12]
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; CHECK: stw r5, sp[11]
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; CHECK: mov r4, r0
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; CHECK: ldaw r5, sp[1]
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; CHECK: ldc r2, 40
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; CHECK: mov r0, r5
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; CHECK: bl memcpy
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; CHECK: mov r0, r5
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; CHECK: bl f1
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; CHECK: mov r0, r4
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; CHECK: ldw r5, sp[11]
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; CHECK: ldw r4, sp[12]
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; CHECK: retsp 13
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%struct.st1 = type { [10 x i32] }
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declare void @f1(%struct.st1*) nounwind
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define i32 @f1Test(i32 %i, %struct.st1* byval %s1) nounwind {
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entry:
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call void @f1(%struct.st1* %s1) nounwind
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ret i32 %i
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}
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; CHECK-LABEL: f2Test
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; CHECK: extsp 4
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; CHECK: stw lr, sp[1]
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; CHECK: stw r2, sp[3]
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; CHECK: stw r3, sp[4]
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; CHECK: ldw r0, r0[0]
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; CHECK: stw r0, sp[2]
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; CHECK: ldaw r2, sp[2]
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; CHECK: mov r0, r1
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; CHECK: mov r1, r2
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; CHECK: bl f2
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; CHECK: ldw lr, sp[1]
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; CHECK: ldaw sp, sp[4]
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; CHECK: retsp 0
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%struct.st2 = type { i32 }
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declare void @f2(i32, %struct.st2*) nounwind
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define void @f2Test(%struct.st2* byval %s2, i32 %i, ...) nounwind {
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entry:
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call void @f2(i32 %i, %struct.st2* %s2)
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ret void
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}
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