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Annotate SSE float conversions with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
fea666b540
commit
f2914c3b2b
@ -1436,11 +1436,13 @@ multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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X86MemOperand x86memop, string asm> {
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let neverHasSideEffects = 1 in {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
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Sched<[WriteCvtI2F]>;
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let mayLoad = 1 in
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src),
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
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Sched<[WriteCvtI2FLd, ReadAfterLd]>;
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} // neverHasSideEffects = 1
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}
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@ -1740,13 +1742,15 @@ let neverHasSideEffects = 1 in {
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def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
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(ins FR64:$src1, FR64:$src2),
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
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IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
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IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2F]>;
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let mayLoad = 1 in
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def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
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(ins FR64:$src1, f64mem:$src2),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RM>,
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XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
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XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
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@ -1755,26 +1759,28 @@ def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))],
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IIC_SSE_CVT_Scalar_RR>;
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IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
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def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))],
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IIC_SSE_CVT_Scalar_RM>,
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XD,
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Requires<[UseSSE2, OptForSize]>;
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Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
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def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
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IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
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IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
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Sched<[WriteCvtF2F]>;
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def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss
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VR128:$src1, sse_load_f64:$src2))],
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IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
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IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
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@ -1782,13 +1788,15 @@ def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
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IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
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IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
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Sched<[WriteCvtF2F]>;
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def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss
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VR128:$src1, sse_load_f64:$src2))],
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IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
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IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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// Convert scalar single to scalar double
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@ -1798,13 +1806,15 @@ def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
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(ins FR32:$src1, FR32:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RR>,
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XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
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XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2F]>;
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let mayLoad = 1 in
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def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
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(ins FR32:$src1, f32mem:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RM>,
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XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
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XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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def : Pat<(f64 (fextend FR32:$src)),
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@ -1823,12 +1833,12 @@ def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))],
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IIC_SSE_CVT_Scalar_RR>, XS,
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Requires<[UseSSE2]>;
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Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
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def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (extloadf32 addr:$src))],
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IIC_SSE_CVT_Scalar_RM>, XS,
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Requires<[UseSSE2, OptForSize]>;
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Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
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// extload f32 -> f64. This matches load+fextend because we have a hack in
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// the isel (PreprocessForFPConvert) that can introduce loads after dag
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@ -1845,57 +1855,61 @@ def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
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IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
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IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
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Sched<[WriteCvtF2F]>;
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def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
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IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
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IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
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def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtss2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
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IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
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IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
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Sched<[WriteCvtF2F]>;
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def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
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"cvtss2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
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IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
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IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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// Convert packed single/double fp to doubleword
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def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>, VEX;
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IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
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def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX;
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IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
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def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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(int_x86_avx_cvt_ps2dq_256 VR256:$src))],
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IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
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IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
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def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
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IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>;
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IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>;
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IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
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// Convert Packed Double FP to Packed DW Integers
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@ -1906,7 +1920,7 @@ let Predicates = [HasAVX] in {
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def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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VEX;
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VEX, Sched<[WriteCvtF2I]>;
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// XMM only
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def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
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@ -1914,18 +1928,20 @@ def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
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def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
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(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
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Sched<[WriteCvtF2ILd]>;
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// YMM only
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def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
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"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
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(int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
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Sched<[WriteCvtF2I]>;
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def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
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"vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
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VEX, VEX_L;
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VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
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def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
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(VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
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}
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@ -1934,11 +1950,11 @@ def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
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IIC_SSE_CVT_PD_RM>;
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IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
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def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
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IIC_SSE_CVT_PD_RR>;
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IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
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// Convert with truncation packed single/double fp to doubleword
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// SSE2 packed instructions with XS prefix
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@ -1946,32 +1962,33 @@ def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>, VEX;
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IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
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def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX;
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IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
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def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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(int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
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IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
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IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
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def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
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(memopv8f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
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IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
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Sched<[WriteCvtF2ILd]>;
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def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>;
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IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
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def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>;
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IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
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|
||||
let Predicates = [HasAVX] in {
|
||||
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
|
||||
@ -2021,7 +2038,7 @@ def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvttpd2dq VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, VEX;
|
||||
IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
|
||||
|
||||
// The assembler can recognize rr 256-bit instructions by seeing a ymm
|
||||
// register, but the same isn't true when using memory operands instead.
|
||||
@ -2034,19 +2051,19 @@ def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvttpd2dqx\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
||||
(memopv2f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, VEX;
|
||||
IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
|
||||
|
||||
// YMM only
|
||||
def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
|
||||
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
|
||||
def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
|
||||
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
|
||||
def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
|
||||
|
||||
@ -2060,12 +2077,13 @@ let Predicates = [HasAVX] in {
|
||||
def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>;
|
||||
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
|
||||
def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
||||
(memopv2f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>;
|
||||
IIC_SSE_CVT_PD_RM>,
|
||||
Sched<[WriteCvtF2ILd]>;
|
||||
|
||||
// Convert packed single to packed double
|
||||
let Predicates = [HasAVX] in {
|
||||
@ -2073,32 +2091,32 @@ let Predicates = [HasAVX] in {
|
||||
def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, TB, VEX;
|
||||
IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
|
||||
def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, TB, VEX;
|
||||
IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
|
||||
def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR256:$dst,
|
||||
(int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
|
||||
def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR256:$dst,
|
||||
(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
|
||||
}
|
||||
|
||||
let Predicates = [UseSSE2] in {
|
||||
def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, TB;
|
||||
IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
|
||||
def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, TB;
|
||||
IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
|
||||
}
|
||||
|
||||
// Convert Packed DW Integers to Packed Double FP
|
||||
@ -2106,30 +2124,33 @@ let Predicates = [HasAVX] in {
|
||||
let neverHasSideEffects = 1, mayLoad = 1 in
|
||||
def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||
[]>, VEX;
|
||||
[]>, VEX, Sched<[WriteCvtI2FLd]>;
|
||||
def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
|
||||
(int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
|
||||
Sched<[WriteCvtI2F]>;
|
||||
def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
|
||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR256:$dst,
|
||||
(int_x86_avx_cvtdq2_pd_256
|
||||
(bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
|
||||
(bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
|
||||
Sched<[WriteCvtI2FLd]>;
|
||||
def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
|
||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR256:$dst,
|
||||
(int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
|
||||
(int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
|
||||
Sched<[WriteCvtI2F]>;
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1, mayLoad = 1 in
|
||||
def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
||||
"cvtdq2pd\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_SSE_CVT_PD_RR>;
|
||||
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
|
||||
def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RM>;
|
||||
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
|
||||
|
||||
// AVX 256-bit register conversion intrinsics
|
||||
let Predicates = [HasAVX] in {
|
||||
@ -2146,7 +2167,7 @@ let Predicates = [HasAVX] in {
|
||||
def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, VEX;
|
||||
IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
|
||||
|
||||
// XMM only
|
||||
def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
|
||||
@ -2155,31 +2176,31 @@ def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtpd2psx\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, VEX;
|
||||
IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
|
||||
|
||||
// YMM only
|
||||
def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
|
||||
"cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
|
||||
IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
|
||||
def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
|
||||
"cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
|
||||
IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
|
||||
def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
(VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
|
||||
|
||||
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
|
||||
IIC_SSE_CVT_PD_RR>;
|
||||
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
|
||||
def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
|
||||
IIC_SSE_CVT_PD_RM>;
|
||||
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
|
||||
|
||||
|
||||
// AVX 256-bit register conversion intrinsics
|
||||
|
||||
Loading…
Reference in New Issue
Block a user