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R600: Use masked read sel for texture instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1379,6 +1379,11 @@ CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
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};
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for (unsigned i = 0; i < 4; i++) {
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if (NewBldVec[i].getOpcode() == ISD::UNDEF)
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// We mask write here to teach later passes that the ith element of this
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// vector is undef. Thus we can use it to reduce 128 bits reg usage,
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// break false dependencies and additionnaly make assembly easier to read.
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RemapSwizzle[i] = 7; // SEL_MASK_WRITE
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if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
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if (C->isZero()) {
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RemapSwizzle[i] = 4; // SEL_0
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@ -93,6 +93,7 @@ main_body:
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}
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; EG-CHECK: @main2
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; EG-CHECK: T{{[0-9]+}}.XY__
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; EG-CHECK: T{{[0-9]+}}.YXZ0
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define void @main2() #0 {
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@ -110,14 +111,12 @@ main_body:
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%10 = extractelement <4 x float> %9, i32 1
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%11 = insertelement <4 x float> undef, float %0, i32 0
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%12 = insertelement <4 x float> %11, float %1, i32 1
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%13 = insertelement <4 x float> %12, float %2, i32 2
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%14 = insertelement <4 x float> %13, float %3, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1)
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%15 = insertelement <4 x float> undef, float %6, i32 0
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%16 = insertelement <4 x float> %15, float %8, i32 1
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%17 = insertelement <4 x float> %16, float %10, i32 2
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%18 = insertelement <4 x float> %17, float 0.000000e+00, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
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call void @llvm.R600.store.swizzle(<4 x float> %12, i32 60, i32 1)
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%13 = insertelement <4 x float> undef, float %6, i32 0
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%14 = insertelement <4 x float> %13, float %8, i32 1
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%15 = insertelement <4 x float> %14, float %10, i32 2
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%16 = insertelement <4 x float> %15, float 0.000000e+00, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %16, i32 0, i32 2)
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ret void
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}
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