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Revert rL292292 since it causes a SEGV on sanitizer-x86_64-linux-fuzzer build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wei Mi
parent
c4a7209e7b
commit
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@ -22,7 +22,6 @@
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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@ -190,9 +189,6 @@ namespace {
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/// This returns true if an interval was modified.
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bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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/// We found a copy which can be moved to its less frequent predecessor.
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bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
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/// If the source of a copy is defined by a
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/// trivial computation, replace the copy by rematerialize the definition.
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bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
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@ -865,167 +861,6 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
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return true;
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}
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/// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
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/// predecessor of BB2, and if B is not redefined on the way from A = B
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/// in BB2 to B = A in BB2, B = A in BB2 is partially redundant if the
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/// execution goes through the path from BB0 to BB2. We may move B = A
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/// to the predecessor without such reversed copy.
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/// So we will transform the program from:
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/// BB0:
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/// A = B; BB1:
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/// ... ...
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/// / \ /
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/// BB2:
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/// ...
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/// B = A;
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///
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/// to:
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///
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/// BB0: BB1:
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/// A = B; ...
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/// ... B = A;
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/// / \ /
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/// BB2:
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/// ...
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///
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/// A special case is when BB0 and BB2 are the same BB which is the only
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/// BB in a loop:
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/// BB1:
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/// ...
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/// BB0/BB2: ----
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/// B = A; |
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/// ... |
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/// A = B; |
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/// |-------
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/// |
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/// We may hoist B = A from BB0/BB2 to BB1.
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///
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/// The major preconditions for correctness to remove such partial
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/// redundancy include:
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/// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
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/// the PHI is defined by the reversed copy A = B in BB0.
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/// 2. No B is referenced from the start of BB2 to B = A.
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/// 3. No B is defined from A = B to the end of BB0.
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/// 4. BB1 has only one successor.
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///
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/// 2 and 4 implicitly ensure B is not live at the end of BB1.
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/// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
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/// colder place, which not only prevent endless loop, but also make sure
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/// the movement of copy is beneficial.
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bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
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MachineInstr &CopyMI) {
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assert(!CP.isPhys());
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if (!CopyMI.isFullCopy())
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return false;
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MachineBasicBlock &MBB = *CopyMI.getParent();
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if (MBB.isEHPad())
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return false;
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if (MBB.pred_size() != 2)
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return false;
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LiveInterval &IntA =
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LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
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LiveInterval &IntB =
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LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
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// A is defined by PHI at the entry of MBB.
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SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
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VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx);
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assert(AValNo && !AValNo->isUnused() && "COPY source not live");
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if (!AValNo->isPHIDef())
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return false;
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// No B is referenced before CopyMI in MBB.
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if (IntB.overlaps(LIS->getMBBStartIdx(&MBB), CopyIdx))
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return false;
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// MBB has two predecessors: one contains A = B so no copy will be inserted
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// for it. The other one will have a copy moved from MBB.
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bool FoundReverseCopy = false;
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MachineBasicBlock *CopyLeftBB = nullptr;
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for (MachineBasicBlock *Pred : MBB.predecessors()) {
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VNInfo *PVal = IntA.getVNInfoBefore(LIS->getMBBEndIdx(Pred));
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MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
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if (!DefMI || !DefMI->isFullCopy()) {
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CopyLeftBB = Pred;
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continue;
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}
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// Check DefMI is a reverse copy and it is in BB Pred.
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if (DefMI->getOperand(0).getReg() != IntA.reg ||
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DefMI->getOperand(1).getReg() != IntB.reg ||
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DefMI->getParent() != Pred) {
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CopyLeftBB = Pred;
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continue;
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}
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// If there is any other def of B after DefMI and before the end of Pred,
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// we need to keep the copy of B = A at the end of Pred if we remove
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// B = A from MBB.
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bool ValB_Changed = false;
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for (auto VNI : IntB.valnos) {
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if (VNI->isUnused())
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continue;
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if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(Pred)) {
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ValB_Changed = true;
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break;
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}
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}
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if (ValB_Changed) {
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CopyLeftBB = Pred;
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continue;
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}
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FoundReverseCopy = true;
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}
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// If no reverse copy is found in predecessors, nothing to do.
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if (!FoundReverseCopy)
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return false;
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// If CopyLeftBB is nullptr, it means every predecessor of MBB contains
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// reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
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// If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
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// update IntA/IntB.
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//
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// If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
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// MBB is hotter than CopyLeftBB.
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if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
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return false;
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// Now ok to move copy.
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if (CopyLeftBB) {
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DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to BB#"
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<< CopyLeftBB->getNumber() << '\t' << CopyMI);
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// Insert new copy to CopyLeftBB.
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auto InsPos = CopyLeftBB->getFirstTerminator();
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MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
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TII->get(TargetOpcode::COPY), IntB.reg)
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.addReg(IntA.reg);
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SlotIndex NewCopyIdx =
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LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
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VNInfo *VNI = IntB.getNextValue(NewCopyIdx, LIS->getVNInfoAllocator());
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IntB.createDeadDef(VNI);
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} else {
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DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from BB#"
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<< MBB.getNumber() << '\t' << CopyMI);
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}
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// Remove CopyMI.
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SlotIndex EndPoint = IntB.Query(CopyIdx.getRegSlot()).endPoint();
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LIS->removeVRegDefAt(IntB, CopyIdx.getRegSlot());
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LIS->RemoveMachineInstrFromMaps(CopyMI);
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CopyMI.eraseFromParent();
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// Extend IntB to the EndPoint of its original live interval.
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SmallVector<SlotIndex, 8> EndPoints;
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EndPoints.push_back(EndPoint);
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LIS->extendToIndices(IntB, EndPoints);
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shrinkToUses(&IntA);
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return true;
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}
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/// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
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/// defining a subregister.
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static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
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@ -1651,12 +1486,6 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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}
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}
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// Try and see if we can partially eliminate the copy by moving the copy to
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// its predecessor.
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if (!CP.isPartial() && !CP.isPhys())
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if (removePartialRedundancy(CP, *CopyMI))
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return true;
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// Otherwise, we are unable to join the intervals.
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DEBUG(dbgs() << "\tInterference!\n");
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Again = true; // May be possible to coalesce later.
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@ -1,51 +0,0 @@
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; RUN: llc -regalloc=greedy -mtriple=x86_64-unknown-linux-gnu < %s -o - | FileCheck %s
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;
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; The test is to check no redundent mov as follows will be generated in %while.body loop.
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; .LBB0_2:
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; movsbl %cl, %ecx
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; movl %edx, %eax ==> This movl can be promoted outside of loop.
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; shll $5, %eax
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; ...
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; movl %eax, %edx
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; jne .LBB0_2
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;
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; CHECK-LABEL: foo:
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; CHECK: [[L0:.LBB0_[0-9]+]]: # %while.body
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; CHECK: movl %[[REGA:.*]], %[[REGB:.*]]
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; CHECK-NOT: movl %[[REGB]], %[[REGA]]
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; CHECK: jne [[L0]]
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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@b = common local_unnamed_addr global i8* null, align 8
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@a = common local_unnamed_addr global i32 0, align 4
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define i32 @foo() local_unnamed_addr {
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entry:
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%t0 = load i8*, i8** @b, align 8
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%t1 = load i8, i8* %t0, align 1
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%cmp4 = icmp eq i8 %t1, 0
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%t2 = load i32, i32* @a, align 4
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br i1 %cmp4, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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br label %while.body
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while.body: ; preds = %while.body.preheader, %while.body
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%t3 = phi i32 [ %add3, %while.body ], [ %t2, %while.body.preheader ]
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%t4 = phi i8 [ %t5, %while.body ], [ %t1, %while.body.preheader ]
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%conv = sext i8 %t4 to i32
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%add = mul i32 %t3, 33
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%add3 = add nsw i32 %add, %conv
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store i32 %add3, i32* @a, align 4
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%t5 = load i8, i8* %t0, align 1
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%cmp = icmp eq i8 %t5, 0
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br i1 %cmp, label %while.end.loopexit, label %while.body
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while.end.loopexit: ; preds = %while.body
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br label %while.end
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while.end: ; preds = %while.end.loopexit, %entry
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%.lcssa = phi i32 [ %t2, %entry ], [ %add3, %while.end.loopexit ]
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ret i32 %.lcssa
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}
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@ -1,122 +0,0 @@
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# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass simple-register-coalescing -o - %s | FileCheck %s
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# Check there is no partial redundent copy left in the loop after register coalescing.
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@b = common local_unnamed_addr global i8* null, align 8
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@a = common local_unnamed_addr global i32 0, align 4
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define i32 @foo() local_unnamed_addr {
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entry:
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%t0 = load i8*, i8** @b, align 8
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%t1 = load i8, i8* %t0, align 1
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%cmp4 = icmp eq i8 %t1, 0
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%t2 = load i32, i32* @a, align 4
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br i1 %cmp4, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader
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%t3 = phi i32 [ %add3, %while.body ], [ %t2, %while.body.preheader ]
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%t4 = phi i8 [ %t5, %while.body ], [ %t1, %while.body.preheader ]
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%conv = sext i8 %t4 to i32
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%add = mul i32 %t3, 33
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%add3 = add nsw i32 %add, %conv
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store i32 %add3, i32* @a, align 4
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%t5 = load i8, i8* %t0, align 1
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%cmp = icmp eq i8 %t5, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%.lcssa = phi i32 [ %t2, %entry ], [ %add3, %while.body ]
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ret i32 %.lcssa
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}
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...
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---
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# Check A = B and B = A copies will not exist in the loop at the same time.
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# CHECK: name: foo
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# CHECK: [[L1:bb.3.while.body]]:
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# CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
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# CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
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# CHECK: JNE_1 %[[L1]]
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name: foo
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64 }
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- { id: 1, class: gr8 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr32 }
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- { id: 4, class: gr8 }
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- { id: 5, class: gr32 }
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- { id: 6, class: gr8 }
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- { id: 7, class: gr32 }
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- { id: 8, class: gr32 }
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- { id: 9, class: gr32 }
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- { id: 10, class: gr32 }
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- { id: 11, class: gr32 }
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- { id: 12, class: gr8 }
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- { id: 13, class: gr32 }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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successors: %bb.4(0x30000000), %bb.1.while.body.preheader(0x50000000)
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%0 = MOV64rm %rip, 1, _, @b, _ :: (dereferenceable load 8 from @b)
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%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
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TEST8rr %12, %12, implicit-def %eflags
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%11 = MOV32rm %rip, 1, _, @a, _ :: (dereferenceable load 4 from @a)
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JNE_1 %bb.1.while.body.preheader, implicit killed %eflags
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bb.4:
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successors: %bb.3.while.end(0x80000000)
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%10 = COPY %11
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JMP_1 %bb.3.while.end
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bb.1.while.body.preheader:
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successors: %bb.2.while.body(0x80000000)
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bb.2.while.body:
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successors: %bb.3.while.end(0x04000000), %bb.2.while.body(0x7c000000)
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%8 = MOVSX32rr8 %12
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%10 = COPY %11
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%10 = SHL32ri %10, 5, implicit-def dead %eflags
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%10 = ADD32rr %10, %11, implicit-def dead %eflags
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%10 = ADD32rr %10, %8, implicit-def dead %eflags
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MOV32mr %rip, 1, _, @a, _, %10 :: (store 4 into @a)
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%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0)
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TEST8rr %12, %12, implicit-def %eflags
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%11 = COPY %10
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JNE_1 %bb.2.while.body, implicit killed %eflags
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JMP_1 %bb.3.while.end
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bb.3.while.end:
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%eax = COPY %10
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RET 0, killed %eax
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...
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