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clean up load and stores alot

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-02-07 05:18:02 +00:00
parent 0538034a82
commit f311e8b901
1 changed files with 13 additions and 143 deletions
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156
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -608,58 +608,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result; return Result;
case ISD::EXTLOAD: case ISD::EXTLOAD:
{ case ISD::ZEXTLOAD:
// Make sure we generate both values.
if (Result != notIn)
ExprMap[N.getValue(1)] = notIn; // Generate the token
else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
SDOperand Chain = N.getOperand(0);
SDOperand Address = N.getOperand(1);
Select(Chain);
switch(Node->getValueType(0)) {
default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
case MVT::i64:
switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
default:
Node->dump();
assert(0 && "Bad extend load!");
case MVT::i64: Opc = Alpha::LDQ; break;
case MVT::i32: Opc = Alpha::LDL; break;
case MVT::i16: Opc = Alpha::LDWU; break;
case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
case MVT::i8: Opc = Alpha::LDBU; break;
}
}
if (Address.getOpcode() == ISD::GlobalAddress)
{
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
}
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address))
{
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
}
else if(Address.getOpcode() == ISD::FrameIndex)
{
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
BuildMI(BB, Opc, 2, Result).addFrameIndex(Tmp1).addReg(Alpha::F31);
}
else
{
long offset;
SelectAddr(Address, Tmp1, offset);
BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
}
return Result;
}
case ISD::SEXTLOAD: case ISD::SEXTLOAD:
{ {
// Make sure we generate both values. // Make sure we generate both values.
@ -677,7 +626,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i64: case MVT::i64:
switch (cast<MVTSDNode>(Node)->getExtraValueType()) { switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Bad sign extend!"); default: Node->dump(); assert(0 && "Bad sign extend!");
case MVT::i32: Opc = Alpha::LDL; break; case MVT::i32: Opc = Alpha::LDL; assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
case MVT::i16: Opc = Alpha::LDWU; assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
case MVT::i8: Opc = Alpha::LDBU; assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
} }
} }
@ -706,53 +658,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result; return Result;
} }
case ISD::ZEXTLOAD:
{
// Make sure we generate both values.
if (Result != notIn)
ExprMap[N.getValue(1)] = notIn; // Generate the token
else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
SDOperand Chain = N.getOperand(0);
SDOperand Address = N.getOperand(1);
Select(Chain);
switch(Node->getValueType(0)) {
default: Node->dump(); assert(0 && "Unknown type to zero extend to.");
case MVT::i64:
switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Bad sign extend!");
case MVT::i16: Opc = Alpha::LDWU; break;
case MVT::i8: Opc = Alpha::LDBU; break;
}
}
if (Address.getOpcode() == ISD::GlobalAddress)
{
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
}
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
}
else if(Address.getOpcode() == ISD::FrameIndex)
{
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
BuildMI(BB, Opc, 2, Result).addFrameIndex(Tmp1).addReg(Alpha::F31);
}
else
{
long offset;
SelectAddr(Address, Tmp1, offset);
BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
}
return Result;
}
case ISD::GlobalAddress: case ISD::GlobalAddress:
AlphaLowering.restoreGP(BB); AlphaLowering.restoreGP(BB);
BuildMI(BB, Alpha::LOAD_ADDR, 1, Result) BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
@ -1383,6 +1288,7 @@ void ISel::Select(SDOperand N) {
BuildMI(BB, Alpha::RETURN, 0); // Just emit a 'ret' instruction BuildMI(BB, Alpha::RETURN, 0); // Just emit a 'ret' instruction
return; return;
case ISD::TRUNCSTORE:
case ISD::STORE: case ISD::STORE:
{ {
SDOperand Chain = N.getOperand(0); SDOperand Chain = N.getOperand(0);
@ -1391,12 +1297,15 @@ void ISel::Select(SDOperand N) {
Select(Chain); Select(Chain);
Tmp1 = SelectExpr(Value); //value Tmp1 = SelectExpr(Value); //value
MVT::ValueType DestType = Value.getValueType(); switch(Value.getValueType()) {
switch(DestType) {
default: assert(0 && "unknown Type in store"); default: assert(0 && "unknown Type in store");
case MVT::i64: Opc = Alpha::STQ; break; case MVT::i64: Opc = Alpha::STQ; break;
case MVT::f64: Opc = Alpha::STT; break; case MVT::f64: Opc = Alpha::STT; break;
case MVT::f32: Opc = Alpha::STS; break; case MVT::f32: Opc = Alpha::STS; break;
case MVT::i1: //FIXME: DAG does not promote this load
case MVT::i8: Opc = Alpha::STB; break;
case MVT::i16: Opc = Alpha::STW; break;
case MVT::i32: Opc = Alpha::STL; break;
} }
if (Address.getOpcode() == ISD::GlobalAddress) if (Address.getOpcode() == ISD::GlobalAddress)
{ {
@ -1406,8 +1315,8 @@ void ISel::Select(SDOperand N) {
} }
else if(Address.getOpcode() == ISD::FrameIndex) else if(Address.getOpcode() == ISD::FrameIndex)
{ {
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex(); Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
BuildMI(BB, Opc, 3).addReg(Tmp1).addFrameIndex(Tmp1).addReg(Alpha::F31); BuildMI(BB, Opc, 3).addReg(Tmp1).addFrameIndex(Tmp2).addReg(Alpha::F31);
} }
else else
{ {
@ -1429,45 +1338,6 @@ void ISel::Select(SDOperand N) {
SelectExpr(N); SelectExpr(N);
return; return;
case ISD::TRUNCSTORE:
{
SDOperand Chain = N.getOperand(0);
SDOperand Value = N.getOperand(1);
SDOperand Address = N.getOperand(2);
Select(Chain);
MVT::ValueType DestType = cast<MVTSDNode>(Node)->getExtraValueType();
switch(DestType) {
default: assert(0 && "unknown Type in store");
case MVT::i1: //FIXME: DAG does not promote this load
case MVT::i8: Opc = Alpha::STB; break;
case MVT::i16: Opc = Alpha::STW; break;
case MVT::i32: Opc = Alpha::STL; break;
}
Tmp1 = SelectExpr(Value); //value
if (Address.getOpcode() == ISD::GlobalAddress)
{
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
}
else if(Address.getOpcode() == ISD::FrameIndex)
{
Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
BuildMI(BB, Opc, 3).addReg(Tmp1).addFrameIndex(Tmp1).addReg(Alpha::F31);
}
else
{
long offset;
SelectAddr(Address, Tmp2, offset);
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
}
return;
}
case ISD::ADJCALLSTACKDOWN: case ISD::ADJCALLSTACKDOWN:
case ISD::ADJCALLSTACKUP: case ISD::ADJCALLSTACKUP:
Select(N.getOperand(0)); Select(N.getOperand(0));