mirror of
https://github.com/RPCS3/llvm.git
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Convert a few tests to use llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
parent
27a2741354
commit
f314160e32
@ -1,67 +0,0 @@
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;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \
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;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \
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;; RUN: -filetype=obj %s -o - | \
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;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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;; FIXME: This file needs to be in .s form!
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;; The args to llc are there to constrain the codegen only.
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;;
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;; Ensure no regression on ARM/gcc compatibility for
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;; emitting explicit symbol relocs for nonexternal symbols
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;; versus section symbol relocs (with offset) -
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;;
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;; Default llvm behavior is to emit as section symbol relocs nearly
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;; everything that is not an undefined external. Unfortunately, this
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;; diverges from what codesourcery ARM/gcc does!
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;;
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;; Tests that reloc to _MergedGlobals show up as explicit symbol reloc
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target triple = "armv7-none-linux-gnueabi"
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@var_tls = thread_local global i32 1
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@var_tls_double = thread_local global double 1.000000e+00
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@var_static = internal global i32 1
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@var_static_double = internal global double 1.000000e+00
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@var_global = global i32 1
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@var_global_double = global double 1.000000e+00
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declare i32 @mystrlen(i8* nocapture %s) nounwind
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declare void @myhextochar(i32 %n, i8* nocapture %buffer)
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declare void @__aeabi_read_tp() nounwind
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declare void @__nacl_read_tp() nounwind
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define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
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entry:
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switch i32 %argc, label %bb3 [
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i32 555, label %bb
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i32 6666, label %bb2
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]
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bb: ; preds = %entry
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store volatile i32 11, i32* @var_tls, align 4
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store volatile double 2.200000e+01, double* @var_tls_double, align 8
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store volatile i32 33, i32* @var_static, align 4
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store volatile double 4.400000e+01, double* @var_static_double, align 8
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store volatile i32 55, i32* @var_global, align 4
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store volatile double 6.600000e+01, double* @var_global_double, align 8
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br label %bb3
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bb2: ; preds = %entry
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ret i32 add (i32 add (i32 add (i32 ptrtoint (i32* @var_tls to i32), i32 add (i32 ptrtoint (i32* @var_static to i32), i32 ptrtoint (i32* @var_global to i32))), i32 ptrtoint (double* @var_tls_double to i32)), i32 add (i32 ptrtoint (double* @var_static_double to i32), i32 ptrtoint (double* @var_global_double to i32)))
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bb3: ; preds = %bb, %entry
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tail call void @exit(i32 55) noreturn nounwind
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unreachable
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}
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declare void @exit(i32) noreturn nounwind
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; OBJ: Relocations [
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; OBJ: Section {{.*}} .rel.text {
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; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals
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; OBJ: }
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; OBJ: ]
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26
test/MC/ARM/elf-reloc-01.s
Normal file
26
test/MC/ARM/elf-reloc-01.s
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@ -0,0 +1,26 @@
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// RUN: llvm-mc -triple=armv7-linux-gnueabi \
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// RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \
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// RUN: -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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// Ensure no regression on ARM/gcc compatibility for
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// emitting explicit symbol relocs for nonexternal symbols
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// versus section symbol relocs (with offset) -
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//
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// Default llvm behavior is to emit as section symbol relocs nearly
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// everything that is not an undefined external. Unfortunately, this
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// diverges from what codesourcery ARM/gcc does!
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//
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// Tests that reloc to _MergedGlobals show up as explicit symbol reloc
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movw r2, :lower16:_MergedGlobals
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_MergedGlobals:
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.long 1
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// OBJ: Relocations [
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// OBJ: Section {{.*}} .rel.text {
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// OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals
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// OBJ: }
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// OBJ: ]
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@ -1,48 +0,0 @@
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;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \
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;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \
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;; RUN: -filetype=obj %s -o - | \
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;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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;; FIXME: This file needs to be in .s form!
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;; The args to llc are there to constrain the codegen only.
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;;
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;; Ensure no regression on ARM/gcc compatibility for
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;; emitting explicit symbol relocs for nonexternal symbols
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;; versus section symbol relocs (with offset) -
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;;
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;; Default llvm behavior is to emit as section symbol relocs nearly
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;; everything that is not an undefined external. Unfortunately, this
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;; diverges from what codesourcery ARM/gcc does!
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;;
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;; Tests that reloc to .L.str* show up as explicit symbols
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target triple = "armv7-none-linux-gnueabi"
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@.str = private constant [7 x i8] c"@null\0A\00", align 4
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@.str1 = private constant [8 x i8] c"@write\0A\00", align 4
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@.str2 = private constant [13 x i8] c"hello worldn\00", align 4
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@.str3 = private constant [7 x i8] c"@exit\0A\00", align 4
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declare i32 @mystrlen(i8* nocapture %s) nounwind readonly
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declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind
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define i32 @main() nounwind {
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entry:
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%0 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind
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%1 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind
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%2 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind
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%3 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind
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tail call void @exit(i32 55) noreturn nounwind
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unreachable
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}
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declare i32 @write(...)
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declare void @exit(i32) noreturn nounwind
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;; OBJ: Relocations [
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;; OBJ: Section {{.*}} .rel.text {
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;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
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;; OBJ: }
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;; OBJ: ]
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27
test/MC/ARM/elf-reloc-02.s
Normal file
27
test/MC/ARM/elf-reloc-02.s
Normal file
@ -0,0 +1,27 @@
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// RUN: llvm-mc -triple=armv7-linux-gnueabi \
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// RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \
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// RUN: -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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// Ensure no regression on ARM/gcc compatibility for
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// emitting explicit symbol relocs for nonexternal symbols
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// versus section symbol relocs (with offset) -
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//
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// Default llvm behavior is to emit as section symbol relocs nearly
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// everything that is not an undefined external. Unfortunately, this
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// diverges from what codesourcery ARM/gcc does!
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//
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// Tests that reloc to .L.str* show up as explicit symbols
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movw r1, :lower16:.L.str
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movt r1, :upper16:.L.str
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.section .rodata,"a",%progbits
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.L.str:
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.asciz "@null\n"
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// OBJ: Relocations [
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// OBJ: Section {{.*}} .rel.text {
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// OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str
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// OBJ: }
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// OBJ: ]
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@ -1,95 +0,0 @@
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;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \
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;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \
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;; RUN: -filetype=obj %s -o - | \
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;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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;; FIXME: This file needs to be in .s form!
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;; The args to llc are there to constrain the codegen only.
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;;
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;; Ensure no regression on ARM/gcc compatibility for
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;; emitting explicit symbol relocs for nonexternal symbols
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;; versus section symbol relocs (with offset) -
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;;
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;; Default llvm behavior is to emit as section symbol relocs nearly
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;; everything that is not an undefined external. Unfortunately, this
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;; diverges from what codesourcery ARM/gcc does!
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;;
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;; Verifies that internal constants appear as explict symbol relocs
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target triple = "armv7-none-linux-gnueabi"
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@startval = global i32 5
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@vtable = internal constant [10 x i32 (...)*] [i32 (...)* bitcast (i32 ()* @foo0 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo1 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo2 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo3 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo4 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo5 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo6 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo7 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo8 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo9 to i32 (...)*)]
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declare i32 @mystrlen(i8* nocapture %s) nounwind readonly
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declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind
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define internal i32 @foo0() nounwind readnone {
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entry:
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ret i32 0
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}
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define internal i32 @foo1() nounwind readnone {
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entry:
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ret i32 1
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}
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define internal i32 @foo2() nounwind readnone {
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entry:
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ret i32 2
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}
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define internal i32 @foo3() nounwind readnone {
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entry:
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ret i32 3
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}
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define internal i32 @foo4() nounwind readnone {
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entry:
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ret i32 4
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}
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define internal i32 @foo5() nounwind readnone {
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entry:
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ret i32 55
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}
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define internal i32 @foo6() nounwind readnone {
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entry:
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ret i32 6
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}
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define internal i32 @foo7() nounwind readnone {
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entry:
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ret i32 7
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}
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define internal i32 @foo8() nounwind readnone {
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entry:
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ret i32 8
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}
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define internal i32 @foo9() nounwind readnone {
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entry:
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ret i32 9
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}
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define i32 @main() nounwind {
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entry:
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%0 = load i32, i32* @startval, align 4
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%1 = getelementptr inbounds [10 x i32 (...)*], [10 x i32 (...)*]* @vtable, i32 0, i32 %0
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%2 = load i32 (...)*, i32 (...)** %1, align 4
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%3 = tail call i32 (...) %2() nounwind
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tail call void @exit(i32 %3) noreturn nounwind
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unreachable
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}
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declare void @exit(i32) noreturn nounwind
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;; OBJ: Relocations [
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;; OBJ: Section {{.*}} .rel.text {
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;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable
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;; OBJ: }
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;; OBJ: ]
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27
test/MC/ARM/elf-reloc-03.s
Normal file
27
test/MC/ARM/elf-reloc-03.s
Normal file
@ -0,0 +1,27 @@
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// RUN: llvm-mc -triple=armv7-linux-gnueabi \
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// RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \
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// RUN: -filetype=obj %s -o - | \
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// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
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// Ensure no regression on ARM/gcc compatibility for
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// emitting explicit symbol relocs for nonexternal symbols
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// versus section symbol relocs (with offset) -
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//
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// Default llvm behavior is to emit as section symbol relocs nearly
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// everything that is not an undefined external. Unfortunately, this
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// diverges from what codesourcery ARM/gcc does!
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//
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// Verifies that internal constants appear as explict symbol relocs
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movw r1, :lower16:vtable
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.section .data.rel.ro.local,"aw",%progbits
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vtable:
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.long 0
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// OBJ: Relocations [
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// OBJ: Section {{.*}} .rel.text {
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// OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable
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// OBJ: }
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// OBJ: ]
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@ -1,45 +0,0 @@
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; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic \
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; RUN: -filetype=obj -o - | llvm-readobj -s -sd -r -t | \
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; RUN: FileCheck %s
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; FIXME: This file needs to be in .s form!
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; We want to test relocatable thumb function call,
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; but ARMAsmParser cannot handle "bl foo(PLT)" yet
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n32"
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target triple = "thumbv7-none--gnueabi"
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define void @foo() nounwind {
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entry:
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ret void
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}
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define void @bar() nounwind {
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entry:
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call void @foo()
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ret void
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}
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; make sure that bl 0 <foo> (fff7feff) is correctly encoded
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; CHECK: Sections [
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; CHECK: SectionData (
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; CHECK: 0000: 704780B5 FFF7FEFF 80BD
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; CHECK: )
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; CHECK: ]
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; CHECK: Relocations [
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; CHECK-NEXT: Section {{.*}} .rel.text {
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; CHECK-NEXT: 0x4 R_ARM_THM_CALL foo 0x0
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; CHECK-NEXT: }
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; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
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; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
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; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0
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; CHECK-NEXT: }
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; CHECK-NEXT: ]
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; make sure foo is thumb function: bit 0 = 1
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; CHECK: Symbols [
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; CHECK: Symbol {
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; CHECK: Name: foo
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; CHECK-NEXT: Value: 0x1
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44
test/MC/ARM/elf-thumbfunc-reloc2.s
Normal file
44
test/MC/ARM/elf-thumbfunc-reloc2.s
Normal file
@ -0,0 +1,44 @@
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// RUN: llvm-mc %s -triple=thumbv7-linux-gnueabi -relocation-model=pic \
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// RUN: -filetype=obj -o - | llvm-readobj -s -sd -r -t | \
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// RUN: FileCheck %s
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// We want to test relocatable thumb function call.
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.thumb_func
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foo:
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.fnstart
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bx lr
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.cantunwind
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.fnend
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.align 1
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bar:
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.fnstart
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push {r7, lr}
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bl foo(PLT)
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pop {r7, pc}
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.cantunwind
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.fnend
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// make sure that bl 0 <foo> (fff7feff) is correctly encoded
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// CHECK: Sections [
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// CHECK: SectionData (
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// CHECK: 0000: 704780B5 FFF7FEFF 80BD
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// CHECK: )
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// CHECK: ]
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// CHECK: Relocations [
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// CHECK-NEXT: Section {{.*}} .rel.text {
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// CHECK-NEXT: 0x4 R_ARM_THM_CALL foo 0x0
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// CHECK-NEXT: }
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// CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
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// CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
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// CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0
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// CHECK-NEXT: }
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// CHECK-NEXT: ]
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// make sure foo is thumb function: bit 0 = 1
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// CHECK: Symbols [
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// CHECK: Symbol {
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// CHECK: Name: foo
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// CHECK-NEXT: Value: 0x1
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