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[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields

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V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields.  This was simply not used in the decoder until now.

Fixes <rdar://problem/17402661>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-06-24 01:42:32 +00:00
parent 68cda26497
commit f36c3de849
2 changed files with 8 additions and 1 deletions
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3
lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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@ -1620,7 +1620,8 @@ static int readVVVV(struct InternalInstruction* insn) {
int vvvv;
if (insn->vectorExtensionType == TYPE_EVEX)
vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]));
else if (insn->vectorExtensionType == TYPE_VEX_3B)
vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
else if (insn->vectorExtensionType == TYPE_VEX_2B)

6
test/MC/Disassembler/X86/avx-512.txt
View File

@ -39,6 +39,12 @@
# CHECK: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2}
0x62 0xf2 0xfd 0x4a 0x92 0x0c 0x86
# CHECK: vpslld $16, %zmm21, %zmm22
0x62 0xb1 0x4d 0x40 0x72 0xf5 0x10
# CHECK: vpord %zmm22, %zmm21, %zmm23
0x62 0xa1 0x55 0x40 0xeb 0xfe
#####################################################
# MASK INSTRUCTIONS #
#####################################################