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[ARM] Selection for MVE VMOVN
The adds both VMOVNt and VMOVNb instruction selection from the appropriate shuffles. We detect shuffle masks of the form: 0, N, 2, N+2, 4, N+4, ... or 0, N+1, 2, N+3, 4, N+5, ... ISel will also try the opposite patterns, with inputs reversed. These are selected to VMOVNt and VMOVNb respectively. Differential Revision: https://reviews.llvm.org/D68283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Green
@@ -4,23 +4,7 @@
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define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: vmovn32_trunc1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov r0, s9
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov r0, s10
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov r0, s11
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnt.i32 q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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@@ -31,23 +15,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc2(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: vmovn32_trunc2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov r0, s9
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov r0, s6
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov r0, s10
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov r0, s11
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnt.i32 q1, q0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <4 x i32> %src1, <4 x i32> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
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@@ -58,39 +27,7 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_trunc1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.8 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.8 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q2[1]
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.8 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.8 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.8 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q2[3]
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; CHECK-NEXT: vmov.8 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.8 q0[7], r0
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.8 q0[8], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.8 q0[9], r0
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; CHECK-NEXT: vmov.u16 r0, q2[5]
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; CHECK-NEXT: vmov.8 q0[10], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.8 q0[11], r0
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; CHECK-NEXT: vmov.u16 r0, q2[6]
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; CHECK-NEXT: vmov.8 q0[12], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.8 q0[13], r0
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; CHECK-NEXT: vmov.u16 r0, q2[7]
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; CHECK-NEXT: vmov.8 q0[14], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.8 q0[15], r0
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; CHECK-NEXT: vmovnt.i16 q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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@@ -101,39 +38,8 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vmovn16_trunc2(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_trunc2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.8 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q2[0]
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; CHECK-NEXT: vmov.8 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q2[1]
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; CHECK-NEXT: vmov.8 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.8 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.8 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.8 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q2[3]
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; CHECK-NEXT: vmov.8 q0[7], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.8 q0[8], r0
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.8 q0[9], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.8 q0[10], r0
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; CHECK-NEXT: vmov.u16 r0, q2[5]
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; CHECK-NEXT: vmov.8 q0[11], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.8 q0[12], r0
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; CHECK-NEXT: vmov.u16 r0, q2[6]
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; CHECK-NEXT: vmov.8 q0[13], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.8 q0[14], r0
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; CHECK-NEXT: vmov.u16 r0, q2[7]
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; CHECK-NEXT: vmov.8 q0[15], r0
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; CHECK-NEXT: vmovnt.i16 q1, q0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src1, <8 x i16> %src2, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>
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@@ -297,23 +203,7 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vmovn16_t1(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_t1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q2[6]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnt.i32 q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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@@ -323,23 +213,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vmovn16_t2(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_t2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q2[0]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q2[6]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnt.i32 q1, q0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>
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@@ -349,23 +224,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vmovn16_b1(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_b1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q2[6]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnb.i32 q1, q0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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@@ -427,23 +287,7 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: vmovn16_b4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q2[1]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q2[3]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q2[5]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q2[7]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmovnb.i32 q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7>
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@@ -454,39 +298,7 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vmovn8_b1(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: vmovn8_b1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u8 r0, q0[0]
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.8 q0[0], r0
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; CHECK-NEXT: vmov.u8 r0, q1[0]
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; CHECK-NEXT: vmov.8 q0[1], r0
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; CHECK-NEXT: vmov.u8 r0, q2[2]
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: vmov.u8 r0, q1[2]
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; CHECK-NEXT: vmov.8 q0[3], r0
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; CHECK-NEXT: vmov.u8 r0, q2[4]
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; CHECK-NEXT: vmov.8 q0[4], r0
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; CHECK-NEXT: vmov.u8 r0, q1[4]
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; CHECK-NEXT: vmov.8 q0[5], r0
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; CHECK-NEXT: vmov.u8 r0, q2[6]
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; CHECK-NEXT: vmov.8 q0[6], r0
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; CHECK-NEXT: vmov.u8 r0, q1[6]
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; CHECK-NEXT: vmov.8 q0[7], r0
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; CHECK-NEXT: vmov.u8 r0, q2[8]
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; CHECK-NEXT: vmov.8 q0[8], r0
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; CHECK-NEXT: vmov.u8 r0, q1[8]
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; CHECK-NEXT: vmov.8 q0[9], r0
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; CHECK-NEXT: vmov.u8 r0, q2[10]
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; CHECK-NEXT: vmov.8 q0[10], r0
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; CHECK-NEXT: vmov.u8 r0, q1[10]
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; CHECK-NEXT: vmov.8 q0[11], r0
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; CHECK-NEXT: vmov.u8 r0, q2[12]
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; CHECK-NEXT: vmov.8 q0[12], r0
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; CHECK-NEXT: vmov.u8 r0, q1[12]
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; CHECK-NEXT: vmov.8 q0[13], r0
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; CHECK-NEXT: vmov.u8 r0, q2[14]
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; CHECK-NEXT: vmov.8 q0[14], r0
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; CHECK-NEXT: vmov.u8 r0, q1[14]
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; CHECK-NEXT: vmov.8 q0[15], r0
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; CHECK-NEXT: vmovnt.i16 q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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@@ -496,39 +308,8 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @vmovn8_b2(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: vmovn8_b2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.u8 r0, q1[0]
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; CHECK-NEXT: vmov.8 q0[0], r0
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; CHECK-NEXT: vmov.u8 r0, q2[0]
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; CHECK-NEXT: vmov.8 q0[1], r0
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; CHECK-NEXT: vmov.u8 r0, q1[2]
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: vmov.u8 r0, q2[2]
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; CHECK-NEXT: vmov.8 q0[3], r0
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; CHECK-NEXT: vmov.u8 r0, q1[4]
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; CHECK-NEXT: vmov.8 q0[4], r0
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; CHECK-NEXT: vmov.u8 r0, q2[4]
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; CHECK-NEXT: vmov.8 q0[5], r0
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||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[6]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[8]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[10]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[10]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[12]
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[12]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[14]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[14]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmovnt.i16 q1, q0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>
|
||||
@@ -538,39 +319,8 @@ entry:
|
||||
define arm_aapcs_vfpcc <16 x i8> @vmovn8_t1(<16 x i8> %src1, <16 x i8> %src2) {
|
||||
; CHECK-LABEL: vmovn8_t1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[0]
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[2]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[4]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[5]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[6]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[7]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[8]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[9]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[10]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[11]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[12]
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[13]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[14]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[15]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmovnb.i16 q1, q0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
|
||||
@@ -664,39 +414,7 @@ entry:
|
||||
define arm_aapcs_vfpcc <16 x i8> @vmovn8_t4(<16 x i8> %src1, <16 x i8> %src2) {
|
||||
; CHECK-LABEL: vmovn8_t4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[0]
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[1]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[3]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[5]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[7]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[9]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[10]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[11]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[12]
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[13]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[14]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[15]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmovnb.i16 q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>
|
||||
|
||||
Reference in New Issue
Block a user