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ARM sched model: Add integer load/store instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
755d1295a5
commit
f3a2329d33
@ -1340,6 +1340,215 @@ let SchedModel = SwiftModel in {
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def : WriteRes<WriteDiv, [SwiftUnitDiv]>; // Workaround.
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def : InstRW < [],
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(instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
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// 4.2.19 Integer Load Single Element
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// 4.2.20 Integer Load Signextended
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def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
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let Latency = 3;
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}
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def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
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let Latency = 4;
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}
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def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01,
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SwiftUnitP01]> {
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let Latency = 4;
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}
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def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> {
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let Latency = 3;
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}
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def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2,
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SwiftUnitP01]> {
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let Latency = 3;
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}
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def SwiftWrBackOne : SchedWriteRes<[]> {
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let Latency = 1;
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let NumMicroOps = 0;
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}
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def SwiftWriteLdFour : SchedWriteRes<[]> {
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let Latency = 4;
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let NumMicroOps = 0;
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}
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// Not accurate.
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def : InstRW<[SwiftWriteP2ThreeCycle],
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(instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
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"t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
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"tLDR(r|i|spi|pci|pciASM)")>;
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def : InstRW<[SwiftWriteP2ThreeCycle],
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(instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>;
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def : InstRW<[SwiftWriteP2P01FourCyle],
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(instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
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"t2LDRpci_pic", "tLDRS(B|H)")>;
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def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne],
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(instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
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"LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
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"t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
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def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne],
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(instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
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"LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>;
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// 4.2.21 Integer Dual Load
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// Not accurate.
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def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour],
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(instregex "t2LDRDi8", "LDRD$")>;
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def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne],
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(instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
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// 4.2.22 Integer Load, Multiple
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// NumReg = 1 .. 16
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foreach Lat = 3-25 in {
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def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
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let Latency = Lat;
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}
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def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { let Latency = Lat; }
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}
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// Predicate.
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foreach NumAddr = 1-16 in {
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def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(MI) == "#NumAddr>;
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}
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def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; }
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def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>;
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def SwiftWriteLM : SchedWriteVariant<[
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SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>,
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SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy]>,
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SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy]>,
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SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy]>,
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SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy]>,
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SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy]>,
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SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy]>,
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SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy]>,
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SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy]>,
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SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy]>,
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SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy]>,
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SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy,
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SwiftWriteLM15Cy]>,
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SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy,
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SwiftWriteLM15Cy, SwiftWriteLM16Cy]>,
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SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy,
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SwiftWriteLM15Cy, SwiftWriteLM16Cy,
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SwiftWriteLM17Cy]>,
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SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5Cy, SwiftWriteLM6Cy,
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SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM12Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy,
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SwiftWriteLM15Cy, SwiftWriteLM16Cy,
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SwiftWriteLM17Cy, SwiftWriteLM18Cy]>,
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// Unknow number of registers, just use resources for two registers.
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SchedVar<NoSchedPred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
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SwiftWriteLM5CyNo, SwiftWriteLM6CyNo,
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SwiftWriteLM7CyNo, SwiftWriteLM8CyNo,
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SwiftWriteLM9CyNo, SwiftWriteLM10CyNo,
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SwiftWriteLM11CyNo, SwiftWriteLM12CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM15CyNo, SwiftWriteLM16CyNo,
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SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]>
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]> { let Variadic=1; }
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def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB],
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(instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
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"(t|sys)LDM(IA|DA|DB|IB)$")>;
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def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM],
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(instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
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"LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
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def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
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(instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>;
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// 4.2.23 Integer Store, Single Element
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def : InstRW<[SwiftWriteP2],
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(instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
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"t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2],
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(instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
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"STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
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"STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
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"t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
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// 4.2.24 Integer Store, Dual
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def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle],
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(instregex "STRD$", "t2STRDi8")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2,
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SwiftWriteP01OneCycle],
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(instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
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// 4.2.25 Integer Store, Multiple
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def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
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let Latency = 0;
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}
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foreach NumAddr = 1-16 in {
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def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>;
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}
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def SwiftWriteSTM : SchedWriteVariant<[
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SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>,
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SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>,
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SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>,
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SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>,
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SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>,
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SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>,
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SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>,
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SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>,
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SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>,
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SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>,
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SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>,
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SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>,
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SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>,
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SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>,
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SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>,
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// Unknow number of registers, just use resources for two registers.
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SchedVar<NoSchedPred, [SwiftWriteSTM2]>
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]>;
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def : InstRW<[SwiftWriteSTM],
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(instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
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(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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"PUSH", "tPUSH")>;
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// 4.2.26 Branch
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def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
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def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
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