diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index c6cfc4b9348..7e8e9893e9e 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -66,6 +66,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   setOperationAction(ISD::SEXTLOAD, MVT::i8,  Expand);
   setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
   
+  setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
+
   setOperationAction(ISD::FREM, MVT::f32, Expand);
   setOperationAction(ISD::FREM, MVT::f64, Expand);
   
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 557da82d1d6..bb2162b4809 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1822,7 +1822,6 @@ void AlphaISel::Select(SDOperand N) {
       } else { //ISD::TRUNCSTORE
         switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
         default: assert(0 && "unknown Type in store");
-        case MVT::i1: //FIXME: DAG does not promote this load
         case MVT::i8: Opc = Alpha::STB; break;
         case MVT::i16: Opc = Alpha::STW; break;
         case MVT::i32: Opc = Alpha::STL; break;