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Remove simple regalloc. It has bit rotted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
d7bd78e36e
commit
f436463dbd
@ -32,7 +32,6 @@ namespace {
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(void) llvm::createDeadMachineInstructionElimPass();
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(void) llvm::createSimpleRegisterAllocator();
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(void) llvm::createLocalRegisterAllocator();
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(void) llvm::createLinearScanRegisterAllocator();
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(void) llvm::createPBQPRegisterAllocator();
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@ -87,12 +87,6 @@ namespace llvm {
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///
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FunctionPass *createRegisterAllocator();
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/// SimpleRegisterAllocation Pass - This pass converts the input machine code
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/// from SSA form to use explicit registers by spilling every register. Wow,
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/// great policy huh?
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///
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FunctionPass *createSimpleRegisterAllocator();
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/// LocalRegisterAllocation Pass - This pass register allocates the input code
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/// a basic block at a time, yielding code better than the simple register
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/// allocator, but not as good as a global allocator.
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@ -46,7 +46,6 @@ add_llvm_library(LLVMCodeGen
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RegAllocLinearScan.cpp
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RegAllocLocal.cpp
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RegAllocPBQP.cpp
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RegAllocSimple.cpp
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RegisterCoalescer.cpp
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RegisterScavenging.cpp
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ScheduleDAG.cpp
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@ -1,261 +0,0 @@
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//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a simple register allocator. *Very* simple: It immediate
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// spills every value right after it is computed, and it reloads all used
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// operands from the spill area to temporary registers before each instruction.
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// It does not keep values in registers across instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <map>
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using namespace llvm;
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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namespace {
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static RegisterRegAlloc
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simpleRegAlloc("simple", "simple register allocator",
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createSimpleRegisterAllocator);
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class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
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public:
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static char ID;
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RegAllocSimple() : MachineFunctionPass(&ID) {}
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private:
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MachineFunction *MF;
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const TargetMachine *TM;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
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// these values are spilled
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std::map<unsigned, int> StackSlotForVirtReg;
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// RegsUsed - Keep track of what registers are currently in use. This is a
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// bitset.
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std::vector<bool> RegsUsed;
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// RegClassIdx - Maps RegClass => which index we can take a register
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// from. Since this is a simple register allocator, when we need a register
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// of a certain class, we just take the next available one.
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std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
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public:
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virtual const char *getPassName() const {
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return "Simple Register Allocator";
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}
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/// runOnMachineFunction - Register allocate the whole function
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bool runOnMachineFunction(MachineFunction &Fn);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// AllocateBasicBlock - Register allocate the specified basic block.
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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/// getStackSpaceFor - This returns the offset of the specified virtual
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/// register on the stack, allocating space if necessary.
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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/// Given a virtual register, return a compatible physical register that is
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/// currently unused.
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///
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/// Side effect: marks that register as being used until manually cleared
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///
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unsigned getFreeReg(unsigned virtualReg);
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/// Moves value from memory into that register
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unsigned reloadVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned VirtReg);
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/// Saves reg value on the stack (maps virtual register to stack value)
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg);
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};
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char RegAllocSimple::ID = 0;
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}
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/// getStackSpaceFor - This allocates space for the specified virtual
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/// register to be held on the stack.
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int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
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const TargetRegisterClass *RC) {
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// Find the location VirtReg would belong...
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std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
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if (I != StackSlotForVirtReg.end())
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return I->second; // Already has space allocated?
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// Allocate a new stack object for this spill location...
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int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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// Assign the slot...
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StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
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return FrameIdx;
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}
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unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
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TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
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#ifndef NDEBUG
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TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
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#endif
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while (1) {
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unsigned regIdx = RegClassIdx[RC]++;
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assert(RI+regIdx != RE && "Not enough registers!");
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unsigned PhysReg = *(RI+regIdx);
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if (!RegsUsed[PhysReg]) {
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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return PhysReg;
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}
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}
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}
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unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg) {
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIdx = getStackSpaceFor(VirtReg, RC);
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unsigned PhysReg = getFreeReg(VirtReg);
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// Add move instruction(s)
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++NumLoads;
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TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
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return PhysReg;
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}
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void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg) {
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIdx = getStackSpaceFor(VirtReg, RC);
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// Add move instruction(s)
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++NumStores;
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TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
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}
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void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// loop over each instruction
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for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
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// Made to combat the incorrect allocation of r2 = add r1, r1
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std::map<unsigned, unsigned> Virt2PhysRegMap;
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RegsUsed.resize(TRI->getNumRegs());
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// This is a preliminary pass that will invalidate any registers that are
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// used by the instruction (including implicit uses).
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const TargetInstrDesc &Desc = MI->getDesc();
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const unsigned *Regs;
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if (Desc.ImplicitUses) {
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for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
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RegsUsed[*Regs] = true;
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}
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if (Desc.ImplicitDefs) {
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for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
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RegsUsed[*Regs] = true;
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MF->getRegInfo().setPhysRegUsed(*Regs);
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}
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}
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// Loop over uses, move from memory into registers.
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned virtualReg = (unsigned) MO.getReg();
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DEBUG({
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errs() << "op: " << MO << "\n" << "\t inst[" << i << "]: ";
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MI->print(errs(), TM);
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});
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// make sure the same virtual register maps to the same physical
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// register in any given instruction
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unsigned physReg = Virt2PhysRegMap[virtualReg];
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if (physReg == 0) {
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if (MO.isDef()) {
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unsigned TiedOp;
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if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
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physReg = getFreeReg(virtualReg);
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} else {
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// must be same register number as the source operand that is
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// tied to. This maps a = b + c into b = b + c, and saves b into
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// a's spot.
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assert(MI->getOperand(TiedOp).isReg() &&
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MI->getOperand(TiedOp).getReg() &&
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MI->getOperand(TiedOp).isUse() &&
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"Two address instruction invalid!");
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physReg = MI->getOperand(TiedOp).getReg();
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}
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spillVirtReg(MBB, next(MI), virtualReg, physReg);
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} else {
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physReg = reloadVirtReg(MBB, MI, virtualReg);
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Virt2PhysRegMap[virtualReg] = physReg;
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}
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}
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MO.setReg(physReg);
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DEBUG(errs() << "virt: " << virtualReg
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<< ", phys: " << MO.getReg() << "\n");
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}
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}
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RegClassIdx.clear();
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RegsUsed.clear();
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}
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
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DEBUG(errs() << "Machine Function\n");
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MF = &Fn;
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TM = &MF->getTarget();
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TRI = TM->getRegisterInfo();
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TII = TM->getInstrInfo();
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// Loop over all of the basic blocks, eliminating virtual register references
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB)
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AllocateBasicBlock(*MBB);
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StackSlotForVirtReg.clear();
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return true;
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}
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FunctionPass *llvm::createSimpleRegisterAllocator() {
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return new RegAllocSimple();
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}
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