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R600/SI: remove GPR*AlignEncode
It's much easier to specify the encoding with tablegen directly. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
777962fddf
commit
f4632b58c7
@ -33,15 +33,6 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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};
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} // End namespace llvm
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@ -42,9 +42,6 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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const MCSubtargetInfo &STI;
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MCContext &Ctx;
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/// \brief Encode a sequence of registers with the correct alignment.
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unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
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/// \brief Can this operand also contain immediate values?
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bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
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@ -65,14 +62,6 @@ public:
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/// \returns the encoding for an MCOperand.
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virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// \brief Encoding for when 2 consecutive registers are used
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virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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/// \brief Encoding for when 4 consectuive registers are used
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virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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};
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} // End anonymous namespace
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@ -212,24 +201,3 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Custom Operand Encodings
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//===----------------------------------------------------------------------===//
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unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
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unsigned shift) const {
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unsigned regCode = MRI.getEncodingValue(MI.getOperand(OpNo).getReg());
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return (regCode & 0xff) >> shift;
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}
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unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
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unsigned OpNo ,
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SmallVectorImpl<MCFixup> &Fixup) const {
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return GPRAlign(MI, OpNo, 1);
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}
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unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
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unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const {
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return GPRAlign(MI, OpNo, 2);
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}
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@ -129,12 +129,12 @@ class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<6> SBASE;
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bits<7> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE;
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let Inst{14-9} = SBASE{6-1};
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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@ -292,7 +292,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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bits<1> ADDR64;
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bits<1> LDS;
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bits<8> VADDR;
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bits<5> SRSRC;
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bits<7> SRSRC;
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bits<1> SLC;
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bits<1> TFE;
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bits<8> SOFFSET;
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@ -307,7 +307,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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@ -330,7 +330,7 @@ class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
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bits<4> DFMT;
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bits<3> NFMT;
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bits<8> VADDR;
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bits<5> SRSRC;
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bits<7> SRSRC;
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bits<1> SLC;
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bits<1> TFE;
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bits<8> SOFFSET;
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@ -346,7 +346,7 @@ class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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@ -370,8 +370,8 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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bits<1> LWE;
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bits<1> SLC;
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bits<8> VADDR;
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bits<5> SRSRC;
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bits<5> SSAMP;
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bits<7> SRSRC;
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bits<7> SSAMP;
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let Inst{11-8} = DMASK;
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let Inst{12} = UNORM;
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@ -385,8 +385,8 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{31-26} = 0x3c;
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC;
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let Inst{57-53} = SSAMP;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{57-53} = SSAMP{6-2};
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let VM_CNT = 1;
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let EXP_CNT = 1;
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@ -53,16 +53,6 @@ def SIOperand {
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int VCC = 0x6A;
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}
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class GPR4Align <RegisterClass rc> : Operand <vAny> {
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let EncoderMethod = "GPR4AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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class GPR2Align <RegisterClass rc> : Operand <iPTR> {
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let EncoderMethod = "GPR2AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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include "SIInstrFormats.td"
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//===----------------------------------------------------------------------===//
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@ -128,13 +118,13 @@ class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
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multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
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def _IMM : SMRD <
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op, 1, (outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
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(ins SReg_64:$sbase, i32imm:$offset),
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asm#" $dst, $sbase, $offset", []
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>;
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def _SGPR : SMRD <
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op, 0, (outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
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(ins SReg_64:$sbase, SReg_32:$soff),
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asm#" $dst, $sbase, $soff", []
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>;
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}
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@ -276,7 +266,7 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
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(outs),
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(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
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[]> {
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@ -288,7 +278,7 @@ class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
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i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
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i1imm:$tfe, SSrc_32:$soffset),
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asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, "
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#"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
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@ -301,7 +291,7 @@ class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
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@ -315,7 +305,7 @@ class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
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GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
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SReg_256:$srsrc, SReg_128:$ssamp),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
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[]> {
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