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Refactor aliased packed logical instructions, also add
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
02ba9e19c7
commit
f4f4bad696
@ -404,13 +404,14 @@ multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, ValueType vt,
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X86MemOperand x86memop, PatFrag mem_frag,
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Domain d> {
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Domain d, bit MayLoad = 0> {
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let isCommutable = 1 in
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
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(mem_frag addr:$src2)))],d>;
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let mayLoad = MayLoad in
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
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(mem_frag addr:$src2)))],d>;
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}
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/// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
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@ -666,50 +667,36 @@ def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
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/// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
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///
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multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode, int NoPat = 0,
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bit MayLoad = 0, bit Commutable = 1> {
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def PSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
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!if(NoPat, []<dag>,
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[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))])> {
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let isCommutable = Commutable;
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SDNode OpNode, bit MayLoad = 0> {
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let isAsmParserOnly = 1 in {
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
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f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
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defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
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f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
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VEX_4V;
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}
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def PDrr : PDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
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!if(NoPat, []<dag>,
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[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))])> {
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let isCommutable = Commutable;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
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f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
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def PSrm : PSI<opc, MRMSrcMem, (outs FR32:$dst),
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(ins FR32:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
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!if(NoPat, []<dag>,
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[(set FR32:$dst, (OpNode FR32:$src1,
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(memopfsf32 addr:$src2)))])> {
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let mayLoad = MayLoad;
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}
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def PDrm : PDI<opc, MRMSrcMem, (outs FR64:$dst),
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(ins FR64:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
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!if(NoPat, []<dag>,
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[(set FR64:$dst, (OpNode FR64:$src1,
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(memopfsf64 addr:$src2)))])> {
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let mayLoad = MayLoad;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
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f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
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}
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}
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// Alias bitwise logical operations using SSE logical ops on packed FP values.
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let Constraints = "$src1 = $dst" in {
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defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
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defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
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defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
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defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
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defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
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defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
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let neverHasSideEffects = 1 in
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defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>;
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}
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let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
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/// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
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/// vector forms.
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@ -10244,3 +10244,67 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc5,0xe9,0x5d,0x6c,0xcb,0xfc]
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vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vandps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x54,0xf2]
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vandps %xmm2, %xmm4, %xmm6
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// CHECK: vandpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x54,0xf2]
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vandpd %xmm2, %xmm4, %xmm6
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// CHECK: vandps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x54,0x6c,0xcb,0xfc]
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vandps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x54,0x6c,0xcb,0xfc]
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vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vorps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x56,0xf2]
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vorps %xmm2, %xmm4, %xmm6
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// CHECK: vorpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x56,0xf2]
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vorpd %xmm2, %xmm4, %xmm6
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// CHECK: vorps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x56,0x6c,0xcb,0xfc]
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vorps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x56,0x6c,0xcb,0xfc]
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vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vxorps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x57,0xf2]
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vxorps %xmm2, %xmm4, %xmm6
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// CHECK: vxorpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x57,0xf2]
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vxorpd %xmm2, %xmm4, %xmm6
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// CHECK: vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x57,0x6c,0xcb,0xfc]
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vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x57,0x6c,0xcb,0xfc]
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vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vandnps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x55,0xf2]
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vandnps %xmm2, %xmm4, %xmm6
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// CHECK: vandnpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x55,0xf2]
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vandnpd %xmm2, %xmm4, %xmm6
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// CHECK: vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x55,0x6c,0xcb,0xfc]
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vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x55,0x6c,0xcb,0xfc]
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vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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@ -296,3 +296,67 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
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// CHECK: encoding: [0xc5,0x19,0x5d,0x54,0xcb,0xfc]
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vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vandps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x54,0xe2]
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vandps %xmm10, %xmm14, %xmm12
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// CHECK: vandpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x54,0xe2]
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vandpd %xmm10, %xmm14, %xmm12
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// CHECK: vandps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x54,0x54,0xcb,0xfc]
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vandps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x54,0x54,0xcb,0xfc]
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vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vorps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x56,0xe2]
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vorps %xmm10, %xmm14, %xmm12
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// CHECK: vorpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x56,0xe2]
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vorpd %xmm10, %xmm14, %xmm12
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// CHECK: vorps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x56,0x54,0xcb,0xfc]
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vorps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x56,0x54,0xcb,0xfc]
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vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vxorps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x57,0xe2]
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vxorps %xmm10, %xmm14, %xmm12
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// CHECK: vxorpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x57,0xe2]
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vxorpd %xmm10, %xmm14, %xmm12
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// CHECK: vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x57,0x54,0xcb,0xfc]
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vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x57,0x54,0xcb,0xfc]
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vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vandnps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x55,0xe2]
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vandnps %xmm10, %xmm14, %xmm12
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// CHECK: vandnpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x55,0xe2]
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vandnpd %xmm10, %xmm14, %xmm12
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// CHECK: vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x55,0x54,0xcb,0xfc]
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vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x55,0x54,0xcb,0xfc]
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vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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