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[mips] Reorder template parameters. Remove class shift_rotate_imm32 and
shift_rotate_imm64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171513 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
c55bd47105
commit
f53b78f5bf
@ -34,11 +34,7 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Shifts
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// 64-bit shift instructions.
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let DecoderNamespace = "Mips64" in {
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class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>:
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shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>;
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multiclass Atomic2Ops64<PatFrag Op> {
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def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
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@ -102,37 +98,41 @@ def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
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def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
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def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
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def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>;
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def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>;
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def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>;
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def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
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def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
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def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
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def DSLL : shift_rotate_imm<"dsll", shamt, CPU64Regs, shl, immZExt6>,
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SRA_FM<0x38, 0>;
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def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64Regs, srl, immZExt6>,
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SRA_FM<0x3a, 0>;
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def DSRA : shift_rotate_imm<"dsra", shamt, CPU64Regs, sra, immZExt6>,
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SRA_FM<0x3b, 0>;
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def DSLLV : shift_rotate_reg<"dsllv", CPU64Regs, shl>, SRLV_FM<0x14, 0>;
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def DSRLV : shift_rotate_reg<"dsrlv", CPU64Regs, srl>, SRLV_FM<0x16, 0>;
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def DSRAV : shift_rotate_reg<"dsrav", CPU64Regs, sra>, SRLV_FM<0x17, 0>;
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def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64Regs>, SRA_FM<0x3c, 0>;
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def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64Regs>, SRA_FM<0x3e, 0>;
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def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64Regs>, SRA_FM<0x3f, 0>;
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}
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// Rotate Instructions
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let Predicates = [HasMips64r2, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>;
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def DROTR : shift_rotate_imm<"drotr", shamt, CPU64Regs, rotr, immZExt6>,
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SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", CPU64Regs, rotr>, SRLV_FM<0x16, 1>;
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}
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let DecoderNamespace = "Mips64" in {
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/// Load and Store Instructions
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/// aligned
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defm LB64 : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>;
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defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>;
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defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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@ -340,6 +340,8 @@ class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
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[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
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let isCommutable = isComm;
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let isReMaterializable = 1;
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string BaseOpcode;
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string Arch;
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}
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// Arithmetic and logical instructions with 2 register operands.
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@ -353,7 +355,7 @@ class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
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}
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// Arithmetic Multiply ADD/SUB
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class MArithR<string opstr, SDNode op, bit isComm = 0> :
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class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
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InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(opstr, "\t$rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> {
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@ -371,17 +373,15 @@ class LogicNOR<string opstr, RegisterClass RC>:
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}
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// Shifts
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class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
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RegisterClass RC, SDPatternOperator OpNode> :
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class shift_rotate_imm<string opstr, Operand ImmOpnd,
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RegisterClass RC, SDPatternOperator OpNode = null_frag,
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SDPatternOperator PF = null_frag> :
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InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
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!strconcat(opstr, "\t$rd, $rt, $shamt"),
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[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
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// 32-bit shift instructions.
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class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
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shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
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class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
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class shift_rotate_reg<string opstr, RegisterClass RC,
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SDPatternOperator OpNode = null_frag>:
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InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
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!strconcat(opstr, "\t$rd, $rt, $rs"),
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[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
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@ -403,20 +403,23 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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}
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// Memory Load/Store
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class Load<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
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class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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Operand MemOpnd> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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let canFoldAsLoad = 1;
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}
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class Store<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
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class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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Operand MemOpnd> :
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InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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}
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multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> {
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multiclass LoadM<string opstr, RegisterClass RC,
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SDPatternOperator OpNode = null_frag> {
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def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
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def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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@ -424,7 +427,8 @@ multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> {
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}
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}
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multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> {
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multiclass StoreM<string opstr, RegisterClass RC,
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SDPatternOperator OpNode = null_frag> {
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def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
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def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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@ -789,29 +793,30 @@ def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
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def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
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def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
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def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
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def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
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def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
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def SLL : shift_rotate_imm<"sll", shamt, CPURegs, shl, immZExt5>, SRA_FM<0, 0>;
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def SRL : shift_rotate_imm<"srl", shamt, CPURegs, srl, immZExt5>, SRA_FM<2, 0>;
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def SRA : shift_rotate_imm<"sra", shamt, CPURegs, sra, immZExt5>, SRA_FM<3, 0>;
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def SLLV : shift_rotate_reg<"sllv", CPURegs, shl>, SRLV_FM<4, 0>;
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def SRLV : shift_rotate_reg<"srlv", CPURegs, srl>, SRLV_FM<6, 0>;
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def SRAV : shift_rotate_reg<"srav", CPURegs, sra>, SRLV_FM<7, 0>;
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// Rotate Instructions
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let Predicates = [HasMips32r2, HasStdEnc] in {
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def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
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def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
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def ROTR : shift_rotate_imm<"rotr", shamt, CPURegs, rotr, immZExt5>,
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SRA_FM<2, 1>;
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def ROTRV : shift_rotate_reg<"rotrv", CPURegs, rotr>, SRLV_FM<6, 1>;
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}
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/// Load and Store Instructions
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/// aligned
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defm LB : LoadM<"lb", sextloadi8, CPURegs>, LW_FM<0x20>;
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defm LBu : LoadM<"lbu", zextloadi8, CPURegs>, LW_FM<0x24>;
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defm LH : LoadM<"lh", sextloadi16, CPURegs>, LW_FM<0x21>;
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defm LHu : LoadM<"lhu", zextloadi16, CPURegs>, LW_FM<0x25>;
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defm LW : LoadM<"lw", load, CPURegs>, LW_FM<0x23>;
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defm SB : StoreM<"sb", truncstorei8, CPURegs>, LW_FM<0x28>;
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defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>;
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defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>;
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defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
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defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
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defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
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defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
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defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
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defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
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defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
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defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
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/// load/store left/right
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defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
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