diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 148e973bb1c..58a261f749f 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -780,30 +780,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
 
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
-  case TargetOpcode::G_UNMERGE_VALUES: {
-    // 
-    LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
-    // Larger extracts are vectors, same-size extracts should be something else
-    // by now (either split up or simplified to a COPY).
-    if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
-      return false;
-
-    I.setDesc(TII.get(AArch64::UBFMXri));
-    MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
-                                      Ty.getSizeInBits() - 1);
-
-    unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
-    BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
-            TII.get(AArch64::COPY))
-        .addDef(I.getOperand(0).getReg())
-        .addUse(DstReg, 0, AArch64::sub_32);
-    RBI.constrainGenericRegister(I.getOperand(0).getReg(),
-                                 AArch64::GPR32RegClass, MRI);
-    I.getOperand(0).setReg(DstReg);
-
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
-
   case TargetOpcode::G_INSERT: {
     LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
     // Larger inserts are vectors, same-size ones should be something else by