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Remove predicated pseudo-instructions.

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These pseudos are no longer needed now that it is possible to represent
predicated instructions in SSA form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-09-05 23:58:04 +00:00
parent 098c6a547f
commit f632d80e0c
2 changed files with 0 additions and 100 deletions
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42
lib/Target/ARM/ARMInstrInfo.td
View File

@ -4016,48 +4016,6 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">;
// Conditional instructions
multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
Instruction irsr,
InstrItinClass iii, InstrItinClass iir,
InstrItinClass iis> {
def ri : ARMPseudoExpand<(outs GPR:$Rd),
(ins GPR:$Rfalse, GPR:$Rn, so_imm:$imm,
pred:$p, cc_out:$s),
4, iii, [],
(iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def rr : ARMPseudoExpand<(outs GPR:$Rd),
(ins GPR:$Rfalse, GPR:$Rn, GPR:$Rm,
pred:$p, cc_out:$s),
4, iir, [],
(irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def rsi : ARMPseudoExpand<(outs GPR:$Rd),
(ins GPR:$Rfalse, GPR:$Rn, so_reg_imm:$shift,
pred:$p, cc_out:$s),
4, iis, [],
(irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, so_reg_reg:$shift,
pred:$p, cc_out:$s),
4, iis, [],
(irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
}
defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm ADDCC : AsI1_bincc_irs<ADDri, ADDrr, ADDrsi, ADDrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
defm SUBCC : AsI1_bincc_irs<SUBri, SUBrr, SUBrsi, SUBrsr,
IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
} // neverHasSideEffects

58
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -774,33 +774,6 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
let Inst{24} = 1;
let Inst{23-21} = op23_21;
}
// Predicated versions.
def CCri : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_imm:$imm,
pred:$p, cc_out:$s), 4, IIC_iALUi, [],
(!cast<Instruction>(NAME#ri) GPRnopc:$Rd,
GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def CCri12 : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPR:$Rn, imm0_4095:$imm,
pred:$p),
4, IIC_iALUi, [],
(!cast<Instruction>(NAME#ri12) GPRnopc:$Rd,
GPR:$Rn, imm0_4095:$imm, pred:$p)>,
RegConstraint<"$Rfalse = $Rd">;
def CCrr : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, rGPR:$Rm,
pred:$p, cc_out:$s), 4, IIC_iALUr, [],
(!cast<Instruction>(NAME#rr) GPRnopc:$Rd,
GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
def CCrs : t2PseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_reg:$Rm,
pred:$p, cc_out:$s), 4, IIC_iALUsi, [],
(!cast<Instruction>(NAME#rs) GPRnopc:$Rd,
GPRnopc:$Rn, t2_so_reg:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
}
/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
@ -3069,37 +3042,6 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
RegConstraint<"$false = $Rd">;
} // isCodeGenOnly = 1
multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
// shifted imm
def ri : t2PseudoExpand<(outs rGPR:$Rd),
(ins rGPR:$Rfalse, rGPR:$Rn, t2_so_imm:$imm,
pred:$p, cc_out:$s),
4, iii, [],
(iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
// register
def rr : t2PseudoExpand<(outs rGPR:$Rd),
(ins rGPR:$Rfalse, rGPR:$Rn, rGPR:$Rm,
pred:$p, cc_out:$s),
4, iir, [],
(irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
// shifted register
def rs : t2PseudoExpand<(outs rGPR:$Rd),
(ins rGPR:$Rfalse, rGPR:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s),
4, iis, [],
(irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
RegConstraint<"$Rfalse = $Rd">;
} // T2I_bincc_irs
defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
} // neverHasSideEffects
//===----------------------------------------------------------------------===//