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[Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAlignmentForCallingConv
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: sdardis, hiraditya, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375407 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -134,9 +134,9 @@ namespace ISD {
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MaybeAlign A = decodeMaybeAlign(OrigAlign);
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return A ? A->value() : 0;
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}
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void setOrigAlign(unsigned A) {
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OrigAlign = encode(Align(A));
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assert(getOrigAlign() == A && "bitfield overflow");
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void setOrigAlign(Align A) {
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OrigAlign = encode(A);
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assert(getOrigAlign() == A.value() && "bitfield overflow");
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}
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unsigned getByValSize() const { return ByValSize; }
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@ -1357,9 +1357,9 @@ public:
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/// Certain targets have context senstive alignment requirements, where one
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/// type has the alignment requirement of another type.
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virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const {
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return DL.getABITypeAlignment(ArgTy);
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virtual Align getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const {
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return Align(DL.getABITypeAlignment(ArgTy));
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}
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/// If true, then instruction selection should seek to shrink the FP constant
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@ -110,7 +110,7 @@ void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
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}
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if (Attrs.hasAttribute(OpIdx, Attribute::Nest))
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Flags.setNest();
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Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty));
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(Arg.Ty)));
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}
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template void
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@ -235,7 +235,7 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
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if (Part == 0) {
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Flags.setSplit();
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} else {
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Flags.setOrigAlign(1);
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Flags.setOrigAlign(Align::None());
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if (Part == NumParts - 1)
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Flags.setSplitEnd();
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}
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@ -268,7 +268,7 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
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if (PartIdx == 0) {
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Flags.setSplit();
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} else {
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Flags.setOrigAlign(1);
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Flags.setOrigAlign(Align::None());
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if (PartIdx == NumParts - 1)
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Flags.setSplitEnd();
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}
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@ -1219,8 +1219,7 @@ bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
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Flags.setNest();
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if (NeedsRegBlock)
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Flags.setInConsecutiveRegs();
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unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
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Flags.setOrigAlign(OriginalAlignment);
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(Arg.Ty)));
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CLI.OutVals.push_back(Arg.Val);
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CLI.OutFlags.push_back(Flags);
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@ -9109,7 +9109,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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// Certain targets (such as MIPS), may have a different ABI alignment
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// for a type depending on the context. Give the target a chance to
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// specify the alignment it wants.
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unsigned OriginalAlignment = getABIAlignmentForCallingConv(ArgTy, DL);
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const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL));
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if (Args[i].Ty->isPointerTy()) {
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Flags.setPointer();
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@ -9220,7 +9220,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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if (NumParts > 1 && j == 0)
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MyFlags.Flags.setSplit();
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else if (j != 0) {
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MyFlags.Flags.setOrigAlign(1);
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MyFlags.Flags.setOrigAlign(Align::None());
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if (j == NumParts - 1)
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MyFlags.Flags.setSplitEnd();
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}
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@ -9607,8 +9607,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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// Certain targets (such as MIPS), may have a different ABI alignment
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// for a type depending on the context. Give the target a chance to
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// specify the alignment it wants.
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unsigned OriginalAlignment =
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TLI->getABIAlignmentForCallingConv(ArgTy, DL);
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const Align OriginalAlignment(
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TLI->getABIAlignmentForCallingConv(ArgTy, DL));
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if (Arg.getType()->isPointerTy()) {
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Flags.setPointer();
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@ -9691,7 +9691,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
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MyFlags.Flags.setSplit();
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// if it isn't first piece, alignment must be 1
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else if (i > 0) {
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MyFlags.Flags.setOrigAlign(1);
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MyFlags.Flags.setOrigAlign(Align::None());
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if (i == NumRegs - 1)
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MyFlags.Flags.setSplitEnd();
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}
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@ -203,8 +203,7 @@ void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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// Even if there is no splitting to do, we still want to replace the
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// original type (e.g. pointer type -> integer).
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auto Flags = OrigArg.Flags[0];
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unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
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Flags.setOrigAlign(OriginalAlignment);
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(OrigArg.Ty)));
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SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
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Flags, OrigArg.IsFixed);
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return;
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@ -216,8 +215,7 @@ void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
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auto Flags = OrigArg.Flags[0];
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unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
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Flags.setOrigAlign(OriginalAlignment);
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(SplitTy)));
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bool NeedsConsecutiveRegisters =
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TLI.functionArgumentNeedsConsecutiveRegisters(
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@ -2237,8 +2237,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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if (!isTypeLegal(ArgTy, ArgVT)) return false;
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ISD::ArgFlagsTy Flags;
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unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(ArgTy)));
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Args.push_back(Op);
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ArgRegs.push_back(Arg);
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@ -2371,8 +2370,7 @@ bool ARMFastISel::SelectCall(const Instruction *I,
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if (!Arg.isValid())
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return false;
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unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Flags.setOrigAlign(Align(DL.getABITypeAlignment(ArgTy)));
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Args.push_back(*i);
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ArgRegs.push_back(Arg);
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@ -16992,16 +16992,15 @@ static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
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}
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/// Return the correct alignment for the current calling convention.
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unsigned
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ARMTargetLowering::getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const {
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Align ARMTargetLowering::getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const {
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const Align ABITypeAlign(DL.getABITypeAlignment(ArgTy));
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if (!ArgTy->isVectorTy())
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return DL.getABITypeAlignment(ArgTy);
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return ABITypeAlign;
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// Avoid over-aligning vector parameters. It would require realigning the
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// stack and waste space for no real benefit.
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return std::min(DL.getABITypeAlignment(ArgTy),
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(unsigned)DL.getStackAlignment().value());
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return std::min(ABITypeAlign, DL.getStackAlignment());
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}
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/// Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
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@ -617,8 +617,8 @@ class VectorType;
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void finalizeLowering(MachineFunction &MF) const override;
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/// Return the correct alignment for the current calling convention.
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unsigned getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const override;
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Align getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const override;
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bool isDesirableToCommuteWithShift(const SDNode *N,
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CombineLevel Level) const override;
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@ -690,7 +690,7 @@ void MipsCallLowering::subTargetRegTypeForCallingConv(
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if (i == 0)
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Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL));
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else
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Flags.setOrigAlign(1);
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Flags.setOrigAlign(Align::None());
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ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
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0);
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@ -304,11 +304,12 @@ class TargetRegisterClass;
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unsigned &NumIntermediates, MVT &RegisterVT) const override;
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/// Return the correct alignment for the current calling convention.
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unsigned getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const override {
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Align getABIAlignmentForCallingConv(Type *ArgTy,
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DataLayout DL) const override {
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const Align ABIAlign(DL.getABITypeAlignment(ArgTy));
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if (ArgTy->isVectorTy())
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return std::min(DL.getABITypeAlignment(ArgTy), 8U);
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return DL.getABITypeAlignment(ArgTy);
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return std::min(ABIAlign, Align(8));
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return ABIAlign;
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}
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ISD::NodeType getExtendForAtomicOps() const override {
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