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ARM memory barrier instructions are not predicable

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-12-14 18:31:20 +00:00
parent 252a0dfa6a
commit f6b2862e81
2 changed files with 20 additions and 3 deletions
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17
lib/Target/ARM/ARMInstrFormats.td
View File

@ -201,6 +201,19 @@ class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
// A few are not predicable
class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin,
string opc, string asm, string cstr,
list<dag> pattern>
: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
let OutOperandList = oops;
let InOperandList = iops;
let AsmString = !strconcat(opc, asm);
let Pattern = pattern;
let isPredicable = 0;
list<Predicate> Predicates = [IsARM];
}
// Same as I except it can optionally modify CPSR. Note it's modeled as
// an input operand since by default it's a zero register. It will
@ -241,6 +254,10 @@ class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern>;
class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern>;
// Ctrl flow instructions
class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1574,8 +1574,8 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
//
// memory barriers protect the atomic sequences
let isPredicable = 0, hasSideEffects = 1 in {
def Int_MemBarrierV7 : AI<(outs), (ins),
let hasSideEffects = 1 in {
def Int_MemBarrierV7 : AInoP<(outs), (ins),
Pseudo, NoItinerary,
"dmb", "",
[(ARMMemBarrier)]>,
@ -1585,7 +1585,7 @@ def Int_MemBarrierV7 : AI<(outs), (ins),
let Inst{3-0} = 0b1111;
}
def Int_SyncBarrierV7 : AI<(outs), (ins),
def Int_SyncBarrierV7 : AInoP<(outs), (ins),
Pseudo, NoItinerary,
"dsb", "",
[(ARMSyncBarrier)]>,