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[x86] enable machine combiner reassociations for scalar single-precision multiplies

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241752 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2015-07-08 22:35:20 +00:00
parent a04933edc1
commit f769239c19
4 changed files with 31 additions and 8 deletions
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6
lib/Target/X86/X86InstrInfo.cpp
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@ -6405,11 +6405,13 @@ static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
// TODO: There are many more machine instruction opcodes to match:
// 1. Other data types (double, integer, vectors)
// 2. Other math / logic operations (mul, and, or)
// 2. Other math / logic operations (and, or)
static bool isAssociativeAndCommutative(unsigned Opcode) {
switch (Opcode) {
case X86::VADDSSrr:
case X86::ADDSSrr:
case X86::VADDSSrr:
case X86::MULSSrr:
case X86::VMULSSrr:
return true;
default:
return false;

4
test/CodeGen/X86/fdiv-combine.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s
; Anything more than one division using a single divisor operand
; should be converted into a reciprocal and multiplication.
@ -17,9 +17,9 @@ define float @div2_arcp(float %x, float %y, float %z) #0 {
; CHECK: # BB#0:
; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: divss %xmm2, %xmm3
; CHECK-NEXT: mulss %xmm3, %xmm0
; CHECK-NEXT: mulss %xmm1, %xmm0
; CHECK-NEXT: mulss %xmm3, %xmm0
; CHECK-NEXT: mulss %xmm3, %xmm0
; CHECK-NEXT: retq
%div1 = fdiv arcp float %x, %z
%mul = fmul arcp float %div1, %y

21
test/CodeGen/X86/machine-combiner.ll
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@ -144,3 +144,24 @@ define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {
ret float %t2
}
; Verify that SSE and AVX scalar single precison multiplies are reassociated.
define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
; SSE-LABEL: reassociate_muls1:
; SSE: # BB#0:
; SSE-NEXT: divss %xmm1, %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: reassociate_muls1:
; AVX: # BB#0:
; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmulss %xmm3, %xmm2, %xmm1
; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%t0 = fdiv float %x0, %x1
%t1 = fmul float %x2, %t0
%t2 = fmul float %x3, %t1
ret float %t2
}

8
test/CodeGen/X86/sqrt-fastmath.ll
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@ -34,11 +34,11 @@ define float @ff(float %f) #0 {
; ESTIMATE: # BB#0:
; ESTIMATE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; ESTIMATE-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm2
; ESTIMATE-NEXT: vmulss %xmm1, %xmm1, %xmm1
; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm1
; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm3
; ESTIMATE-NEXT: vmulss %xmm3, %xmm1, %xmm1
; ESTIMATE-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; ESTIMATE-NEXT: vmulss %xmm0, %xmm2, %xmm2
; ESTIMATE-NEXT: vmulss %xmm2, %xmm1, %xmm1
; ESTIMATE-NEXT: vmulss %xmm1, %xmm0, %xmm1
; ESTIMATE-NEXT: vxorps %xmm2, %xmm2, %xmm2
; ESTIMATE-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0
; ESTIMATE-NEXT: vandnps %xmm1, %xmm0, %xmm0
@ -78,7 +78,7 @@ define float @reciprocal_square_root(float %x) #0 {
; ESTIMATE: # BB#0:
; ESTIMATE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; ESTIMATE-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm2
; ESTIMATE-NEXT: vmulss %xmm1, %xmm1, %xmm1
; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm0
; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm0
; ESTIMATE-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; ESTIMATE-NEXT: vmulss %xmm2, %xmm0, %xmm0