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Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371873 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alexander Timofeev
parent
ebe9e05e29
commit
f884885482
@ -22,7 +22,6 @@
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineOutliner.h"
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@ -1639,28 +1638,6 @@ public:
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return false;
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}
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/// During PHI eleimination lets target to make necessary checks and
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/// insert the copy to the PHI destination register in a target specific
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/// manner.
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virtual MachineInstr *createPHIDestinationCopy(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
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const DebugLoc &DL, Register Src, Register Dst) const {
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return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
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.addReg(Src);
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}
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/// During PHI eleimination lets target to make necessary checks and
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/// insert the copy to the PHI destination register in a target specific
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/// manner.
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virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsPt,
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const DebugLoc &DL, Register Src,
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Register SrcSubReg,
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Register Dst) const {
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return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
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.addReg(Src, 0, SrcSubReg);
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}
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/// Returns a \p outliner::OutlinedFunction struct containing target-specific
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/// information for a set of outlining candidates.
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virtual outliner::OutlinedFunction getOutliningCandidateInfo(
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@ -31,9 +31,7 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Pass.h"
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@ -254,12 +252,11 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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// Insert a register to register copy at the top of the current block (but
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// after any remaining phi nodes) which copies the new incoming register
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// into the phi node destination.
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MachineInstr *PHICopy = nullptr;
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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if (allPhiOperandsUndefined(*MPhi, *MRI))
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// If all sources of a PHI node are implicit_def or undef uses, just emit an
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// implicit_def instead of a copy.
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PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
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else {
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// Can we reuse an earlier PHI node? This only happens for critical edges,
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@ -276,13 +273,15 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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}
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// Give the target possiblity to handle special cases fallthrough otherwise
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PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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IncomingReg, DestReg);
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BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::COPY), DestReg)
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.addReg(IncomingReg);
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}
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// Update live variable information if there is any.
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if (LV) {
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MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
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if (IncomingReg) {
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LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
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@ -303,7 +302,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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// killed. Note that because the value is defined in several places (once
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// each for each incoming block), the "def" block and instruction fields
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// for the VarInfo is not filled in.
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LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);
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LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
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}
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// Since we are going to be deleting the PHI node, if it is the last use of
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@ -313,14 +312,15 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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// If the result is dead, update LV.
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if (isDead) {
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LV->addVirtualRegisterDead(DestReg, *PHICopy);
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LV->addVirtualRegisterDead(DestReg, PHICopy);
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LV->removeVirtualRegisterDead(DestReg, *MPhi);
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}
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}
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// Update LiveIntervals for the new copy or implicit def.
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if (LIS) {
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SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
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SlotIndex DestCopyIndex =
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LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
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SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
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if (IncomingReg) {
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@ -406,9 +406,9 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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if (DefMI->isImplicitDef())
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ImpDefs.insert(DefMI);
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} else {
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NewSrcInstr =
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TII->createPHISourceCopy(opBlock, InsertPos, MPhi->getDebugLoc(),
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SrcReg, SrcSubReg, IncomingReg);
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NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
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TII->get(TargetOpcode::COPY), IncomingReg)
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.addReg(SrcReg, 0, SrcSubReg);
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}
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}
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@ -457,7 +457,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
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}
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} else {
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// We just inserted this copy.
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KillInst = NewSrcInstr;
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KillInst = std::prev(InsertPos);
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}
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}
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assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
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@ -6410,33 +6410,3 @@ bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
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return true;
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}
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}
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MachineInstr *SIInstrInfo::createPHIDestinationCopy(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt,
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const DebugLoc &DL, Register Src, Register Dst) const {
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auto Cur = MBB.begin();
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while (Cur != MBB.end()) {
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if (!Cur->isPHI() && Cur->readsRegister(Dst))
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return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
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++Cur;
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if (Cur == LastPHIIt)
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break;
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}
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return TargetInstrInfo::createPHIDestinationCopy(MBB, LastPHIIt, DL, Src,
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Dst);
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}
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MachineInstr *SIInstrInfo::createPHISourceCopy(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
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const DebugLoc &DL, Register Src, Register SrcSubReg, Register Dst) const {
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if (InsPt != MBB.end() && InsPt->isPseudo() && InsPt->definesRegister(Src)) {
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InsPt++;
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return BuildMI(MBB, InsPt, InsPt->getDebugLoc(), get(TargetOpcode::COPY),
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Dst)
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.addReg(Src, 0, SrcSubReg)
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.addReg(AMDGPU::EXEC, RegState::Implicit);
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}
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return TargetInstrInfo::createPHISourceCopy(MBB, InsPt, DL, Src, SrcSubReg,
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Dst);
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}
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@ -954,17 +954,6 @@ public:
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bool isBasicBlockPrologue(const MachineInstr &MI) const override;
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MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsPt,
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const DebugLoc &DL, Register Src,
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Register Dst) const override;
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MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsPt,
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const DebugLoc &DL, Register Src,
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Register SrcSubReg,
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Register Dst) const override;
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/// Return a partially built integer add instruction without carry.
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/// Caller must add source operands.
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/// For pre-GFX9 it will generate unused carry destination operand.
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@ -400,17 +400,13 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) {
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void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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unsigned CFMask = MI.getOperand(0).getReg();
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MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock::iterator InsPt =
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Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))
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: MBB.begin();
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MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
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.addReg(Exec)
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.add(MI.getOperand(0));
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MachineBasicBlock::iterator InsPt = MBB.begin();
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MachineInstr *NewMI =
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BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
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.addReg(Exec)
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.add(MI.getOperand(0));
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if (LIS)
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LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
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@ -26,8 +26,8 @@ body: |
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# CHECK-LABEL: name: foo
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# CHECK: bb.3:
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# CHECK-NEXT: dead %2:sreg_32_xm0 = IMPLICIT_DEF
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# CHECK-NEXT: %3:sreg_32_xm0 = COPY killed %4
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# CHECK-NEXT: dead %2:sreg_32_xm0 = IMPLICIT_DEF
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# CHECK-NEXT: S_NOP 0, implicit killed %3
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@ -1,54 +0,0 @@
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# RUN: llc -mtriple amdgcn -run-pass livevars -run-pass phi-node-elimination -o - %s | FileCheck %s
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# CHECK-LABEL: phi-cf-test
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# CHECK: bb.0:
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# CHECK: [[COND:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64
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# CHECK: [[IF_SOURCE0:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: [[IF_INPUT_REG:%[0-9]+]]:sreg_64 = COPY killed [[IF_SOURCE0]], implicit $exec
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# CHECK: bb.1:
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# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY killed [[IF_INPUT_REG]]
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# CHECK: SI_END_CF killed [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: bb.2:
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# CHECK: [[IF_SOURCE1:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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# CHECK: [[IF_INPUT_REG]]:sreg_64 = COPY killed [[IF_SOURCE1]], implicit $exec
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...
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---
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name: phi-cf-test
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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liveins: $vgpr0
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%5:vgpr_32(s32) = COPY $vgpr0
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%0:sreg_64 = V_CMP_EQ_U32_e64 0, %5(s32), implicit $exec
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%18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%22:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3(0x80000000)
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%24:sreg_64 = PHI %20, %bb.3, %22, %bb.0
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%23:vgpr_32 = PHI %19, %bb.3, %18, %bb.0
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SI_END_CF %24, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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%3:vgpr_32, dead %10:sreg_64 = nsw V_ADD_I32_e64 1, %23, 0, implicit $exec
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bb.3:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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%4:vgpr_32 = PHI %19, %bb.3, %3, %bb.2, %18, %bb.0
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%15:sreg_32_xm0 = S_MOV_B32 61440
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%16:sreg_32_xm0 = S_MOV_B32 -1
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%17:sreg_128 = REG_SEQUENCE undef %14:sreg_32_xm0, %subreg.sub0, undef %12:sreg_32_xm0, %subreg.sub1, %16, %subreg.sub2, %15, %subreg.sub3
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BUFFER_STORE_DWORD_OFFSET %4, %17, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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%19:vgpr_32 = COPY %4
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%20:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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...
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