RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-13 23:18:58 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[RISCV] MC layer support for the standard RV32M instruction set extension

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Bradbury 2017-11-09 14:46:30 +00:00
parent a4b0c616f6
commit f8c0f51efe
6 changed files with 81 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/RISCV/RISCV.td
View File

@ -13,11 +13,16 @@ include "llvm/Target/Target.td"
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
"Implements RV64">;
def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
"'M' (Integer Multiplication and Division)">;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<"FeatureStdExtM">;
def RV64 : HwMode<"+64bit">;
def RV32 : HwMode<"-64bit">;
def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
"Implements RV64">;
def RV64 : HwMode<"+64bit">;
def RV32 : HwMode<"-64bit">;
//===----------------------------------------------------------------------===//
// Registers, calling conventions, instruction descriptions.

6
lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -399,3 +399,9 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(CallSeqEnd timm:$amt1, timm:$amt2)]>;
} // Defs = [X2], Uses = [X2]
//===----------------------------------------------------------------------===//
// Standard extensions
//===----------------------------------------------------------------------===//
include "RISCVInstrInfoM.td"

28
lib/Target/RISCV/RISCVInstrInfoM.td Normal file
View File

@ -0,0 +1,28 @@
//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions from the standard 'M', Integer
// Multiplication and Division instruction set extension.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtM] in {
def MUL : ALU_rr<0b0000001, 0b000, "mul">;
def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
def DIV : ALU_rr<0b0000001, 0b100, "div">;
def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
def REM : ALU_rr<0b0000001, 0b110, "rem">;
def REMU : ALU_rr<0b0000001, 0b111, "remu">;
} // Predicates = [HasStdExtM]

2
lib/Target/RISCV/RISCVSubtarget.h
View File

@ -30,6 +30,7 @@ class StringRef;
class RISCVSubtarget : public RISCVGenSubtargetInfo {
virtual void anchor();
bool HasStdExtM;
bool HasRV64 = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;
@ -66,6 +67,7 @@ public:
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
bool hasStdExtM() const { return HasStdExtM; }
bool is64Bit() const { return HasRV64; }
MVT getXLenVT() const { return XLenVT; }
unsigned getXLen() const { return XLen; }

3
test/MC/RISCV/rv32i-invalid.s
View File

@ -128,3 +128,6 @@ lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the
# Too few operands
ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Instruction not in the base ISA
mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled

33
test/MC/RISCV/rv32m-valid.s Normal file
View File

@ -0,0 +1,33 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+m -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+m -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+m < %s \
# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \
# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
# CHECK-INST: mul a4, ra, s0
# CHECK: encoding: [0x33,0x87,0x80,0x02]
mul a4, ra, s0
# CHECK-INST: mulh ra, zero, zero
# CHECK: encoding: [0xb3,0x10,0x00,0x02]
mulh x1, x0, x0
# CHECK-INST: mulhsu t0, t2, t1
# CHECK: encoding: [0xb3,0xa2,0x63,0x02]
mulhsu t0, t2, t1
# CHECK-INST: mulhu a5, a4, a3
# CHECK: encoding: [0xb3,0x37,0xd7,0x02]
mulhu a5, a4, a3
# CHECK-INST: div s0, s0, s0
# CHECK: encoding: [0x33,0x44,0x84,0x02]
div s0, s0, s0
# CHECK-INST: divu gp, a0, a1
# CHECK: encoding: [0xb3,0x51,0xb5,0x02]
divu gp, a0, a1
# CHECK-INST: rem s2, s2, s8
# CHECK: encoding: [0x33,0x69,0x89,0x03]
rem s2, s2, s8
# CHECK-INST: remu s2, s2, s8
# CHECK: encoding: [0x33,0x79,0x89,0x03]
remu x18, x18, x24