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Clean up a few 80 column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-06-13 22:54:22 +00:00
parent c0e2607564
commit f921c0fe34
6 changed files with 50 additions and 40 deletions
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4
lib/Target/ARM/ARMBaseInstrInfo.h
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@ -291,8 +291,8 @@ public:
int64_t &Offset1, int64_t &Offset2)const; int64_t &Offset1, int64_t &Offset2)const;
/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
/// be scheduled togther. On some targets if two loads are loading from /// should be scheduled togther. On some targets if two loads are loading from
/// addresses in the same cache line, it's better if they are scheduled /// addresses in the same cache line, it's better if they are scheduled
/// together. This function takes two integers that represent the load offsets /// together. This function takes two integers that represent the load offsets
/// from the common base address. It returns true if it decides it's desirable /// from the common base address. It returns true if it decides it's desirable

6
lib/Target/ARM/ARMInstrInfo.td
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@ -2670,9 +2670,9 @@ def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
let Constraints = "@earlyclobber $Rd" in let Constraints = "@earlyclobber $Rd" in
def MLAv5: ARMPseudoInst<(outs GPR:$Rd), def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
Size4Bytes, IIC_iMAC32, Size4Bytes, IIC_iMAC32,
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
Requires<[IsARM, NoV6]> { Requires<[IsARM, NoV6]> {
bits<4> Ra; bits<4> Ra;
let Inst{15-12} = Ra; let Inst{15-12} = Ra;

10
lib/Target/ARM/ARMInstrNEON.td
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@ -175,7 +175,7 @@ class VLDQQWBPseudo<InstrItinClass itin>
(ins addrmode6:$addr, am6offset:$offset), itin, (ins addrmode6:$addr, am6offset:$offset), itin,
"$addr.addr = $wb">; "$addr.addr = $wb">;
class VLDQQQQPseudo<InstrItinClass itin> class VLDQQQQPseudo<InstrItinClass itin>
: PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src), itin,"">; : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,"">;
class VLDQQQQWBPseudo<InstrItinClass itin> class VLDQQQQWBPseudo<InstrItinClass itin>
: PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
@ -1387,7 +1387,7 @@ class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
: NLdStLn<1, 0b00, op11_8, op7_4, (outs), : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
(ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane), (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
[(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]> { [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
let Rm = 0b1111; let Rm = 0b1111;
} }
class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
@ -3793,7 +3793,8 @@ def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
(ins DPR:$src1, DPR:$Vn, DPR:$Vm), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
N3RegFrm, IIC_VCNTiD, N3RegFrm, IIC_VCNTiD,
"vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[(set DPR:$Vd, (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>; [(set DPR:$Vd,
(v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd), def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
(and DPR:$Vm, (vnotd DPR:$Vd)))), (and DPR:$Vm, (vnotd DPR:$Vd)))),
@ -3803,7 +3804,8 @@ def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
(ins QPR:$src1, QPR:$Vn, QPR:$Vm), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
N3RegFrm, IIC_VCNTiQ, N3RegFrm, IIC_VCNTiQ,
"vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[(set QPR:$Vd, (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>; [(set QPR:$Vd,
(v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd), def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
(and QPR:$Vm, (vnotq QPR:$Vd)))), (and QPR:$Vm, (vnotq QPR:$Vd)))),

9
lib/Target/ARM/ARMInstrThumb.td
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@ -739,9 +739,9 @@ defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
// A8.6.207 & A8.6.205 // A8.6.207 & A8.6.205
defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
t_addrmode_is2, AddrModeT1_2, t_addrmode_is2, AddrModeT1_2,
IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
@ -911,7 +911,8 @@ def tADC : // A8.6.2
// Add immediate // Add immediate
def tADDi3 : // A8.6.4 T1 def tADDi3 : // A8.6.4 T1
T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi, T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
IIC_iALUi,
"add", "\t$Rd, $Rm, $imm3", "add", "\t$Rd, $Rm, $imm3",
[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
bits<3> imm3; bits<3> imm3;

49
lib/Target/ARM/ARMInstrThumb2.td
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@ -1084,7 +1084,7 @@ multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
let Inst{7} = 1; let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate let Inst{5-4} = 0b00; // rotate
} }
def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot), def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> { IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
@ -1788,8 +1788,10 @@ defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>; node:$RHS)>, 1>;
defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
node:$RHS)>>;
// RSB // RSB
defm t2RSB : T2I_rbin_irs <0b1110, "rsb", defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
@ -2005,10 +2007,10 @@ def t2USAT: T2SatI<
let Inst{15} = 0; let Inst{15} = 0;
} }
def t2USAT16: T2SatI< def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary, NoItinerary,
"usat16", "\t$dst, $sat_imm, $Rn", "usat16", "\t$dst, $sat_imm, $Rn",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25-22} = 0b1110; let Inst{25-22} = 0b1110;
let Inst{20} = 0; let Inst{20} = 0;
@ -2861,16 +2863,15 @@ class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
} }
let mayLoad = 1 in { let mayLoad = 1 in {
def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone, def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, $addr", AddrModeNone, Size4Bytes, NoItinerary,
"", []>; "ldrexb", "\t$Rt, $addr", "", []>;
def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone, def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, $addr", AddrModeNone, Size4Bytes, NoItinerary,
"", []>; "ldrexh", "\t$Rt, $addr", "", []>;
def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr), AddrModeNone, def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
Size4Bytes, NoItinerary, AddrModeNone, Size4Bytes, NoItinerary,
"ldrex", "\t$Rt, $addr", "", "ldrex", "\t$Rt, $addr", "", []> {
[]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0000101; let Inst{26-20} = 0b0000101;
let Inst{11-8} = 0b1111; let Inst{11-8} = 0b1111;
@ -2893,12 +2894,14 @@ def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
} }
let mayStore = 1, Constraints = "@earlyclobber $Rd" in { let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
AddrModeNone, Size4Bytes, NoItinerary, (ins rGPR:$Rt, t2addrmode_reg:$addr),
"strexb", "\t$Rd, $Rt, $addr", "", []>; AddrModeNone, Size4Bytes, NoItinerary,
def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), "strexb", "\t$Rd, $Rt, $addr", "", []>;
AddrModeNone, Size4Bytes, NoItinerary, def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
"strexh", "\t$Rd, $Rt, $addr", "", []>; (ins rGPR:$Rt, t2addrmode_reg:$addr),
AddrModeNone, Size4Bytes, NoItinerary,
"strexh", "\t$Rd, $Rt, $addr", "", []>;
def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
AddrModeNone, Size4Bytes, NoItinerary, AddrModeNone, Size4Bytes, NoItinerary,
"strex", "\t$Rd, $Rt, $addr", "", "strex", "\t$Rd, $Rt, $addr", "",

12
lib/Target/ARM/ARMInstrVFP.td
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@ -94,7 +94,8 @@ multiclass vfp_ldst_mult<string asm, bit L_bit,
let Inst{20} = L_bit; let Inst{20} = L_bit;
} }
def DIA_UPD : def DIA_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
variable_ops),
IndexModeUpd, itin_upd, IndexModeUpd, itin_upd,
!strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
let Inst{24-23} = 0b01; // Increment After let Inst{24-23} = 0b01; // Increment After
@ -102,7 +103,8 @@ multiclass vfp_ldst_mult<string asm, bit L_bit,
let Inst{20} = L_bit; let Inst{20} = L_bit;
} }
def DDB_UPD : def DDB_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
variable_ops),
IndexModeUpd, itin_upd, IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
let Inst{24-23} = 0b10; // Decrement Before let Inst{24-23} = 0b10; // Decrement Before
@ -124,7 +126,8 @@ multiclass vfp_ldst_mult<string asm, bit L_bit,
let D = VFPNeonDomain; let D = VFPNeonDomain;
} }
def SIA_UPD : def SIA_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
variable_ops),
IndexModeUpd, itin_upd, IndexModeUpd, itin_upd,
!strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
let Inst{24-23} = 0b01; // Increment After let Inst{24-23} = 0b01; // Increment After
@ -136,7 +139,8 @@ multiclass vfp_ldst_mult<string asm, bit L_bit,
let D = VFPNeonDomain; let D = VFPNeonDomain;
} }
def SDB_UPD : def SDB_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
variable_ops),
IndexModeUpd, itin_upd, IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
let Inst{24-23} = 0b10; // Decrement Before let Inst{24-23} = 0b10; // Decrement Before