RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-29 14:40:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

ptx: add shift instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Che-Liang Chiou 2010-12-06 04:00:03 +00:00
parent f8803fe417
commit f964486771
3 changed files with 92 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
lib/Target/PTX/PTXInstrInfo.td
View File

@ -46,6 +46,11 @@ def MEMii : Operand<i32> {
// PTX Specific Node Definitions // PTX Specific Node Definitions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PTX allow generic 3-reg shifts like shl r0, r1, r2
def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
def PTXexit def PTXexit
: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>; : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
def PTXret def PTXret
@ -66,6 +71,22 @@ multiclass INT3<string opcstr, SDNode opnode> {
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>; [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
} }
// no %type directive, non-communtable
multiclass INT3ntnc<string opcstr, SDNode opnode> {
def rr : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, RRegs32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
def ri : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, i32imm:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
def ir : InstPTX<(outs RRegs32:$d),
(ins i32imm:$a, RRegs32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
}
multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> { multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
def ri : InstPTX<(outs RC:$d), def ri : InstPTX<(outs RC:$d),
(ins MEMri:$a), (ins MEMri:$a),
@ -86,6 +107,12 @@ multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
defm ADD : INT3<"add", add>; defm ADD : INT3<"add", add>;
defm SUB : INT3<"sub", sub>; defm SUB : INT3<"sub", sub>;
///===- Logic and Shift Instructions --------------------------------------===//
defm SHL : INT3ntnc<"shl.b32", PTXshl>;
defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
defm SRA : INT3ntnc<"shr.s32", PTXsra>;
///===- Data Movement and Conversion Instructions -------------------------===// ///===- Data Movement and Conversion Instructions -------------------------===//
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {

22
test/CodeGen/PTX/shl.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -march=ptx | FileCheck %s
define ptx_device i32 @t1(i32 %x, i32 %y) {
; CHECK: shl.b32 r0, r1, r2
%z = shl i32 %x, %y
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t2(i32 %x) {
; CHECK: shl.b32 r0, r1, 3
%z = shl i32 %x, 3
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t3(i32 %x) {
; CHECK: shl.b32 r0, 3, r1
%z = shl i32 3, %x
; CHECK: ret;
ret i32 %z
}

43
test/CodeGen/PTX/shr.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llc < %s -march=ptx | FileCheck %s
define ptx_device i32 @t1(i32 %x, i32 %y) {
; CHECK: shr.u32 r0, r1, r2
%z = lshr i32 %x, %y
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t2(i32 %x) {
; CHECK: shr.u32 r0, r1, 3
%z = lshr i32 %x, 3
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t3(i32 %x) {
; CHECK: shr.u32 r0, 3, r1
%z = lshr i32 3, %x
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t4(i32 %x, i32 %y) {
; CHECK: shr.s32 r0, r1, r2
%z = ashr i32 %x, %y
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t5(i32 %x) {
; CHECK: shr.s32 r0, r1, 3
%z = ashr i32 %x, 3
; CHECK: ret;
ret i32 %z
}
define ptx_device i32 @t6(i32 %x) {
; CHECK: shr.s32 r0, -3, r1
%z = ashr i32 -3, %x
; CHECK: ret;
ret i32 %z
}