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[X86] Add some missing redundant MMX and SSE encodings for disassembler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230165 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-02-22 07:50:41 +00:00
parent 855cb47fae
commit f9c1605d56
3 changed files with 49 additions and 0 deletions
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11
lib/Target/X86/X86InstrMMX.td
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@ -255,6 +255,11 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
[(set VR64:$dst, (bitconvert GR64:$src))],
IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
(ins i64mem:$src), "movd\t{$src, $dst|$dst, $src}",
[], IIC_MMX_MOVQ_RM>, Sched<[WriteLoad]>;
// These are 64 bit moves, but since the OS X assembler doesn't
// recognize a register-register movq, we write them as
// movd.
@ -275,6 +280,12 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
}
} // SchedRW
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
(outs i64mem:$dst), (ins VR64:$src),
"movd\t{$src, $dst|$dst, $src}",
[], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>;
let SchedRW = [WriteLoad] in {
let canFoldAsLoad = 1 in
def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),

17
lib/Target/X86/X86InstrSSE.td
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@ -4734,6 +4734,10 @@ def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
[(set VR128:$dst,
(v2i64 (scalar_to_vector GR64:$src)))],
IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}",
[], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
let isCodeGenOnly = 1 in
def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}",
@ -4755,6 +4759,10 @@ def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
[(set VR128:$dst,
(v2i64 (scalar_to_vector GR64:$src)))],
IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
let isCodeGenOnly = 1 in
def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
@ -4841,6 +4849,15 @@ def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
IIC_SSE_MOVD_ToGP>;
} //SchedRW
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
(ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
[], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
//===---------------------------------------------------------------------===//
// Bitcast FR64 <-> GR64
//

21
test/MC/Disassembler/X86/x86-64.txt
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@ -236,6 +236,27 @@
# CHECK: vmovq %xmm0, %rax
0xc4 0xe1 0xf9 0x7e 0xc0
# CHECK: movd (%rax), %mm0
0x48 0x0f 0x6e 0x00
# CHECK: movd %rax, %mm0
0x48 0x0f 0x6e 0xc0
# CHECK: movd %mm0, (%rax)
0x48 0x0f 0x7e 0x00
# CHECK: movd %mm0, %rax
0x48 0x0f 0x7e 0xc0
# CHECK: movd (%rax), %xmm0
0x66 0x48 0x0f 0x6e 0x00
# CHECK: movd %rax, %xmm0
0x66 0x48 0x0f 0x6e 0xc0
# CHECK: movd %xmm0, (%rax)
0x66 0x48 0x0f 0x7e 0x00
# CHECK: movd %xmm0, %rax
0x66 0x48 0x0f 0x7e 0xc0