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Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.

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Also make the method non-asserting. It will return NULL when given an invalid subreg index.

The method is needed by an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-04-28 16:34:09 +00:00
parent 30590f5023
commit fa4677b483
2 changed files with 13 additions and 14 deletions
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10
include/llvm/Target/TargetRegisterInfo.h
View File

@ -148,6 +148,16 @@ public:
return I;
}
/// getSubRegisterRegClass - Return the register class of subregisters with
/// index SubIdx, or NULL if no such class exists.
const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
assert(SubIdx>0 && "Invalid subregister index");
for (unsigned s = 0; s != SubIdx-1; ++s)
if (!SubRegClasses[s])
return NULL;
return SubRegClasses[SubIdx-1];
}
/// superregclasses_begin / superregclasses_end - Loop over all of
/// the superreg register classes of this register class.
sc_iterator superregclasses_begin() const {

17
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -329,18 +329,6 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
}
}
/// getSubRegisterRegClass - Returns the register class of specified register
/// class' "SubIdx"'th sub-register class.
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
/// getSuperRegisterRegClass - Returns the register class of a superreg A whose
/// "SubIdx"'th sub-register class is the specified register class and whose
/// type matches the specified type.
@ -350,7 +338,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
// Pick the register class of the superegister for this type
for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)
if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
return *I;
assert(false && "Couldn't find the register class");
return 0;
@ -388,7 +376,8 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
// Figure out the register class to create for the destreg.
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
// Figure out the register class to create for the destreg.
// Note that if we're going to directly use an existing register,