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[X86] New pass to change byte and word instructions to zero-extending versions.
Differential Revision: http://reviews.llvm.org/D17032 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260572 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin B. Smith
parent
6d97a8c749
commit
fa502aa703
@ -36,6 +36,7 @@ set(sources
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X86FixupLEAs.cpp
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X86WinEHState.cpp
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X86OptimizeLEAs.cpp
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X86FixupBWInsts.cpp
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)
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add_llvm_target(X86CodeGen ${sources})
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@ -72,6 +72,12 @@ FunctionPass *createX86WinEHStatePass();
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/// must run after prologue/epilogue insertion and before lowering
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/// the MachineInstr to MC.
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FunctionPass *createX86ExpandPseudoPass();
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/// Return a Machine IR pass that selectively replaces
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/// certain byte and word instructions by equivalent 32 bit instructions,
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/// in order to eliminate partial register usage, false dependences on
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/// the upper portions of registers, and to save code size.
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FunctionPass *createX86FixupBWInsts();
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} // End llvm namespace
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#endif
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282
lib/Target/X86/X86FixupBWInsts.cpp
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282
lib/Target/X86/X86FixupBWInsts.cpp
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@ -0,0 +1,282 @@
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//===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines the pass that looks through the machine instructions
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/// late in the compilation, and finds byte or word instructions that
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/// can be profitably replaced with 32 bit instructions that give equivalent
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/// results for the bits of the results that are used. There are two possible
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/// reasons to do this.
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///
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/// One reason is to avoid false-dependences on the upper portions
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/// of the registers. Only instructions that have a destination register
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/// which is not in any of the source registers can be affected by this.
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/// Any instruction where one of the source registers is also the destination
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/// register is unaffected, because it has a true dependence on the source
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/// register already. So, this consideration primarily affects load
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/// instructions and register-to-register moves. It would
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/// seem like cmov(s) would also be affected, but because of the way cmov is
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/// really implemented by most machines as reading both the destination and
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/// and source regsters, and then "merging" the two based on a condition,
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/// it really already should be considered as having a true dependence on the
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/// destination register as well.
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///
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/// The other reason to do this is for potential code size savings. Word
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/// operations need an extra override byte compared to their 32 bit
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/// versions. So this can convert many word operations to their larger
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/// size, saving a byte in encoding. This could introduce partial register
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/// dependences where none existed however. As an example take:
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/// orw ax, $0x1000
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/// addw ax, $3
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/// now if this were to get transformed into
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/// orw ax, $1000
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/// addl eax, $3
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/// because the addl encodes shorter than the addw, this would introduce
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/// a use of a register that was only partially written earlier. On older
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/// Intel processors this can be quite a performance penalty, so this should
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/// probably only be done when it can be proven that a new partial dependence
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/// wouldn't be created, or when your know a newer processor is being
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/// targeted, or when optimizing for minimum code size.
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///
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-fixup-bw-insts"
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// Option to allow this optimization pass to have fine-grained control.
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// This is turned off by default so as not to affect a large number of
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// existing lit tests.
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static cl::opt<bool>
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FixupBWInsts("fixup-byte-word-insts",
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cl::desc("Change byte and word instructions to larger sizes"),
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cl::init(false), cl::Hidden);
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namespace {
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class FixupBWInstPass : public MachineFunctionPass {
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static char ID;
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const char *getPassName() const override {
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return "X86 Byte/Word Instruction Fixup";
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}
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/// \brief Loop over all of the instructions in the basic block
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/// replacing applicable byte or word instructions with better
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/// alternatives.
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void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB) const;
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/// \brief This sets the \p SuperDestReg to the 32 bit super reg
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/// of the original destination register of the MachineInstr
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/// passed in. It returns true if that super register is dead
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/// just prior to \p OrigMI, and false if not.
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/// \pre OrigDestSize must be 8 or 16.
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bool getSuperRegDestIfDead(MachineInstr *OrigMI, unsigned OrigDestSize,
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unsigned &SuperDestReg) const;
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/// \brief Change the MachineInstr \p MI into the equivalent extending load
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/// to 32 bit register if it is safe to do so. Return the replacement
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/// instruction if OK, otherwise return nullptr.
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/// \pre OrigDestSize must be 8 or 16.
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MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, unsigned OrigDestSize,
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MachineInstr *MI) const;
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public:
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FixupBWInstPass() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
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// guide some heuristics.
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// \brief Loop over all of the basic blocks,
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/// replacing byte and word instructions by equivalent 32 bit instructions
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/// where performance or code size can be improved.
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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MachineFunction *MF;
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/// Machine instruction info used throughout the class.
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const X86InstrInfo *TII;
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/// Local member for function's OptForSize attribute.
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bool OptForSize;
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/// Machine loop info used for guiding some heruistics.
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MachineLoopInfo *MLI;
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};
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char FixupBWInstPass::ID = 0;
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}
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FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
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bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
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if (!FixupBWInsts)
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return false;
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this->MF = &MF;
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TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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OptForSize = MF.getFunction()->optForSize();
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MLI = &getAnalysis<MachineLoopInfo>();
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DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
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// Process all basic blocks.
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for (auto &MBB : MF)
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processBasicBlock(MF, MBB);
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DEBUG(dbgs() << "End X86FixupBWInsts\n";);
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return true;
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}
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// TODO: This method of analysis can miss some legal cases, because the
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// super-register could be live into the address expression for a memory
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// reference for the instruction, and still be killed/last used by the
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// instruction. However, the existing query interfaces don't seem to
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// easily allow that to be checked.
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//
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// What we'd really like to know is whether after OrigMI, the
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// only portion of SuperDestReg that is alive is the portion that
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// was the destination register of OrigMI.
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bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
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unsigned OrigDestSize,
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unsigned &SuperDestReg) const {
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unsigned OrigDestReg = OrigMI->getOperand(0).getReg();
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SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
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// Make sure that the sub-register that this instruction has as its
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// destination is the lowest order sub-register of the super-register.
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// If it isn't, then the register isn't really dead even if the
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// super-register is considered dead.
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// This test works because getX86SubSuperRegister returns the low portion
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// register by default when getting a sub-register, so if that doesn't
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// match the original destination register, then the original destination
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// register must not have been the low register portion of that size.
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if (getX86SubSuperRegister(SuperDestReg, OrigDestSize) != OrigDestReg)
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return false;
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MachineBasicBlock::LivenessQueryResult LQR =
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OrigMI->getParent()->computeRegisterLiveness(&TII->getRegisterInfo(),
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SuperDestReg, OrigMI);
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if (LQR != MachineBasicBlock::LQR_Dead)
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return false;
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if (OrigDestSize == 8) {
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// In the case of byte registers, we also have to check that the upper
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// byte register is also dead. That is considered to be independent of
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// whether the super-register is dead.
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unsigned UpperByteReg = getX86SubSuperRegister(SuperDestReg, 8, true);
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LQR = OrigMI->getParent()->computeRegisterLiveness(&TII->getRegisterInfo(),
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UpperByteReg, OrigMI);
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if (LQR != MachineBasicBlock::LQR_Dead)
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return false;
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}
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return true;
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}
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MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
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unsigned OrigDestSize,
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MachineInstr *MI) const {
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unsigned NewDestReg;
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// We are going to try to rewrite this load to a larger zero-extending
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// load. This is safe if all portions of the 32 bit super-register
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// of the original destination register, except for the original destination
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// register are dead. getSuperRegDestIfDead checks that.
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if (!getSuperRegDestIfDead(MI, OrigDestSize, NewDestReg))
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return nullptr;
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// Safe to change the instruction.
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MachineInstrBuilder MIB =
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BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
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unsigned NumArgs = MI->getNumOperands();
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for (unsigned i = 1; i < NumArgs; ++i)
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MIB.addOperand(MI->getOperand(i));
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MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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return MIB;
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}
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void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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// This algorithm doesn't delete the instructions it is replacing
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// right away. By leaving the existing instructions in place, the
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// register liveness information doesn't change, and this makes the
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// analysis that goes on be better than if the replaced instructions
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// were immediately removed.
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//
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// This algorithm always creates a replacement instruction
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// and notes that and the original in a data structure, until the
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// whole BB has been analyzed. This keeps the replacement instructions
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// from making it seem as if the larger register might be live.
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SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
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MachineInstr *NewMI = nullptr;
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MachineInstr *MI = I;
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// See if this is an instruction of the type we are currently looking for.
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switch (MI->getOpcode()) {
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case X86::MOV8rm:
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// Only replace 8 bit loads with the zero extending versions if
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// in an inner most loop and not optimizing for size. This takes
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// an extra byte to encode, and provides limited performance upside.
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if (MachineLoop *ML = MLI->getLoopFor(&MBB)) {
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if (ML->begin() == ML->end() && !OptForSize)
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NewMI = tryReplaceLoad(X86::MOVZX32rm8, 8, MI);
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}
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break;
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case X86::MOV16rm:
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// Always try to replace 16 bit load with 32 bit zero extending.
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// Code size is the same, and there is sometimes a perf advantage
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// from eliminating a false dependence on the upper portion of
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// the register.
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NewMI = tryReplaceLoad(X86::MOVZX32rm16, 16, MI);
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break;
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default:
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// nothing to do here.
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break;
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}
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if (NewMI)
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MIReplacements.push_back(std::make_pair(MI, NewMI));
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}
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while (!MIReplacements.empty()) {
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MachineInstr *MI = MIReplacements.back().first;
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MachineInstr *NewMI = MIReplacements.back().second;
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MIReplacements.pop_back();
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MBB.insert(MI, NewMI);
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MBB.erase(MI);
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}
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}
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@ -279,6 +279,7 @@ void X86PassConfig::addPreEmitPass() {
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addPass(createX86IssueVZeroUpperPass());
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createX86FixupBWInsts());
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addPass(createX86PadShortFunctions());
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addPass(createX86FixupLEAs());
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}
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122
test/CodeGen/X86/fixup-bw-inst.ll
Normal file
122
test/CodeGen/X86/fixup-bw-inst.ll
Normal file
@ -0,0 +1,122 @@
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; RUN: llc -fixup-byte-word-insts -march=x86-64 < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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%struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 }
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; This has byte loads interspersed with byte stores, in a single
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; basic-block loop. The upper portion should be dead, so the movb loads
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; should have been changed into movzbl instead.
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; TODO: The second movb load doesn't get fixed due to register liveness
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; not being accurate enough.
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; CHECK-LABEL: foo1
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; load:
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; CHECK: movzbl
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; store:
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; CHECK: movb
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; load:
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; CHECK: movb
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; store:
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; CHECK: movb
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; CHECK: ret
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define void @foo1(i32 %count,
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%struct.A* noalias nocapture %q,
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%struct.A* noalias nocapture %p)
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nounwind uwtable noinline ssp {
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%1 = icmp sgt i32 %count, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph: ; preds = %0
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%2 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 0
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%3 = getelementptr inbounds %struct.A, %struct.A* %q, i64 0, i32 1
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br label %a4
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a4: ; preds = %4, %.lr.ph
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%i.02 = phi i32 [ 0, %.lr.ph ], [ %a9, %a4 ]
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%.01 = phi %struct.A* [ %p, %.lr.ph ], [ %a10, %a4 ]
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%a5 = load i8, i8* %2, align 1
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%a7 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 0
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store i8 %a5, i8* %a7, align 1
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%a8 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 0, i32 1
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%a6 = load i8, i8* %3, align 1
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store i8 %a6, i8* %a8, align 1
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%a9 = add nsw i32 %i.02, 1
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%a10 = getelementptr inbounds %struct.A, %struct.A* %.01, i64 1
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%exitcond = icmp eq i32 %a9, %count
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br i1 %exitcond, label %._crit_edge, label %a4
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._crit_edge: ; preds = %4, %0
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ret void
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}
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%struct.B = type { i16, i16, i16, i16, i16, i16, i16, i16 }
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; This has word loads interspersed with word stores.
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; The upper portion should be dead, so the movw loads should have
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; been changed into movzwl instead.
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; TODO: The second movw load doesn't get fixed due to register liveness
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; not being accurate enough.
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; CHECK-LABEL: foo2
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; load:
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; CHECK: movzwl
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; store:
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; CHECK: movw
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; load:
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; CHECK: movw
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; store:
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; CHECK: movw
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; CHECK: ret
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define void @foo2(i32 %count,
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%struct.B* noalias nocapture %q,
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%struct.B* noalias nocapture %p)
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nounwind uwtable noinline ssp {
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%1 = icmp sgt i32 %count, 0
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br i1 %1, label %.lr.ph, label %._crit_edge
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.lr.ph: ; preds = %0
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%2 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 0
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%3 = getelementptr inbounds %struct.B, %struct.B* %q, i64 0, i32 1
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br label %a4
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a4: ; preds = %4, %.lr.ph
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%i.02 = phi i32 [ 0, %.lr.ph ], [ %a9, %a4 ]
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%.01 = phi %struct.B* [ %p, %.lr.ph ], [ %a10, %a4 ]
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%a5 = load i16, i16* %2, align 2
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%a7 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 0
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store i16 %a5, i16* %a7, align 2
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%a8 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 0, i32 1
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%a6 = load i16, i16* %3, align 2
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store i16 %a6, i16* %a8, align 2
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%a9 = add nsw i32 %i.02, 1
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%a10 = getelementptr inbounds %struct.B, %struct.B* %.01, i64 1
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%exitcond = icmp eq i32 %a9, %count
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br i1 %exitcond, label %._crit_edge, label %a4
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._crit_edge: ; preds = %4, %0
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ret void
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}
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; This test contains nothing but a simple byte load and store. Since
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; movb encodes smaller, we do not want to use movzbl unless in a tight loop.
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; So this test checks that movb is used.
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; CHECK-LABEL: foo3:
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; CHECK: movb
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; CHECK: movb
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define void @foo3(i8 *%dst, i8 *%src) {
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%t0 = load i8, i8 *%src, align 1
|
||||
store i8 %t0, i8 *%dst, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; This test contains nothing but a simple word load and store. Since
|
||||
; movw and movzwl are the same size, we should always choose to use
|
||||
; movzwl instead.
|
||||
; CHECK-LABEL: foo4:
|
||||
; CHECK: movzwl
|
||||
; CHECK: movw
|
||||
define void @foo4(i16 *%dst, i16 *%src) {
|
||||
%t0 = load i16, i16 *%src, align 2
|
||||
store i16 %t0, i16 *%dst, align 2
|
||||
ret void
|
||||
}
|
||||
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Reference in New Issue
Block a user