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Lower BUILD_VECTOR to SHUFFLE + INSERT_VECTOR_ELT for X86
- If INSERT_VECTOR_ELT is supported (above SSE2, either by custom sequence of legal insn), transform BUILD_VECTOR into SHUFFLE + INSERT_VECTOR_ELT if most of elements could be built from SHUFFLE with few (so far 1) elements being inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166288 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5175,6 +5175,80 @@ X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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SDValue
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X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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// Skip if insert_vec_elt is not supported.
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if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
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return SDValue();
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DebugLoc DL = Op.getDebugLoc();
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unsigned NumElems = Op.getNumOperands();
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SDValue VecIn1;
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SDValue VecIn2;
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SmallVector<unsigned, 4> InsertIndices;
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SmallVector<int, 8> Mask(NumElems, -1);
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for (unsigned i = 0; i != NumElems; ++i) {
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unsigned Opc = Op.getOperand(i).getOpcode();
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if (Opc == ISD::UNDEF)
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continue;
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if (Opc != ISD::EXTRACT_VECTOR_ELT) {
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// Quit if more than 1 elements need inserting.
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if (InsertIndices.size() > 1)
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return SDValue();
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InsertIndices.push_back(i);
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continue;
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}
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SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
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SDValue ExtIdx = Op.getOperand(i).getOperand(1);
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// Quit if extracted from vector of different type.
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if (ExtractedFromVec.getValueType() != VT)
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return SDValue();
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// Quit if non-constant index.
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if (!isa<ConstantSDNode>(ExtIdx))
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return SDValue();
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if (VecIn1.getNode() == 0)
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VecIn1 = ExtractedFromVec;
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else if (VecIn1 != ExtractedFromVec) {
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if (VecIn2.getNode() == 0)
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VecIn2 = ExtractedFromVec;
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else if (VecIn2 != ExtractedFromVec)
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// Quit if more than 2 vectors to shuffle
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return SDValue();
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}
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unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
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if (ExtractedFromVec == VecIn1)
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Mask[i] = Idx;
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else if (ExtractedFromVec == VecIn2)
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Mask[i] = Idx + NumElems;
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}
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if (VecIn1.getNode() == 0)
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return SDValue();
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VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
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SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
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for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
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unsigned Idx = InsertIndices[i];
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NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
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DAG.getIntPtrConstant(Idx));
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}
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return NV;
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}
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SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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@ -5451,6 +5525,11 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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if (LD.getNode())
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return LD;
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// Check for a build vector from mostly shuffle plus few inserting.
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SDValue Sh = buildFromShuffleMostly(Op, DAG);
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if (Sh.getNode())
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return Sh;
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// For SSE 4.1, use insertps to put the high elements into the low element.
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if (getSubtarget()->hasSSE41()) {
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SDValue Result;
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@ -825,9 +825,10 @@ namespace llvm {
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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// Utility functions to help LowerVECTOR_SHUFFLE
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// Utility functions to help LowerVECTOR_SHUFFLE & LowerBUILD_VECTOR
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SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
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SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
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SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
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15
test/CodeGen/X86/buildvec-insertvec.ll
Normal file
15
test/CodeGen/X86/buildvec-insertvec.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind {
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%t0 = fptoui <3 x float> %in to <3 x i8>
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%t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
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%t2 = insertelement <4 x i8> %t1, i8 -1, i32 3
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store <4 x i8> %t2, <4 x i8>* %out, align 4
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ret void
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; CHECK: foo
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; CHECK: cvttps2dq
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; CHECK-NOT: pextrd
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; CHECK: pinsrd
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; CHECK-NEXT: pshufb
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; CHECK: ret
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}
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