From fb61c4384c0ba9a5079689947e2069f7f1780724 Mon Sep 17 00:00:00 2001 From: Roman Shirokiy Date: Fri, 10 Jun 2016 13:12:48 +0000 Subject: [PATCH] Test commit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272393 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/README.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt index 19a18320175..799157c926e 100644 --- a/lib/Target/X86/README.txt +++ b/lib/Target/X86/README.txt @@ -50,8 +50,8 @@ Some isel ideas: 2. Code duplication (addressing mode) during isel. 3. Other ideas from "Register-Sensitive Selection, Duplication, and Sequencing of Instructions". -4. Scheduling for reduced register pressure. E.g. "Minimum Register - Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs" +4. Scheduling for reduced register pressure. E.g. "Minimum Register + Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs" and other related papers. http://citeseer.ist.psu.edu/govindarajan01minimum.html @@ -73,7 +73,7 @@ It appears icc use push for parameter passing. Need to investigate. //===---------------------------------------------------------------------===// The instruction selector sometimes misses folding a load into a compare. The -pattern is written as (cmp reg, (load p)). Because the compare isn't +pattern is written as (cmp reg, (load p)). Because the compare isn't commutative, it is not matched with the load on both sides. The dag combiner should be made smart enough to canonicalize the load into the RHS of a compare when it can invert the result of the compare for free.